AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

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ID 683183
Date 12/18/2017
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Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report x
Hardware Requirements Hardware Setup AD9371 EVM Software Setup Hardware Checkout Methodology for JESD204B Transmitter JESD204B IP Core and DAC Configurations Hardware Checkout Methodology for JESD204B Receiver JESD204B IP Core and Main ADC Configurations Deterministic Latency (Subclass 1) Test Results Test Result Comments Document Revision History for AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Hardware Checkout Methodology for JESD204B Transmitter x
Transmitter Data Link Layer Transmitter Transport Layer Scrambling
Transmitter Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Hardware Checkout Methodology for JESD204B Receiver x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

AD9371 EVM Software Setup

The AD9371 Transceiver evaluation software is used to generate the setup files for the AD9371 device and AD9528 clock generator for JESD204B link operation. For more information about AD9371 Transceiver evaluation software, visit the Analog website.

Setup files for each of the parameter configurations are included in the software installation in the form of predefined profiles. You need to generate the C scripts using the profiles with correct settings for the JESD204B link to operate at the targeted data rate and JESD204B link parameters.

Follow these steps to generate the configuration C scripts via the AD9371 Transceiver evaluation software graphical user interface (GUI):

  1. Start the AD9371 Transceiver Evaluation Software (TES). Figure 3 shows the opening page of TES.
    Figure 3. AD9371 TES interface
  2. In the case when evaluation hardware is not connected, the user can still use the software in demonstration mode by following these steps:
    1. Click Connect (top left corner).
    2. The Zynq board is disconnected message appears; click OK. After clicking OK, the software enters demonstration mode in which a subset of all features is displayed as shown in Figure 4.
  3. The first tab displayed is the Configuration tab. Selecting this tab opens the initial screen, as shown in Figure 4. The following selections are available from this tab:
    1. Device clock frequency
    2. Number of active Rx channels
    3. Number of active Tx channels
    4. Select observation/Sniffer input
    5. Select profiles for Rx, Tx, ORx, and Sniffer Rx
    6. Select Rx, Tx, and SnRx/ORx RF frequency
  4. The AD9371 provides a observation receiver (ORx ADC). The SERDES for main receiver datapath and observation receiver datapath are shared, but they have independent JESD204B framers (For more information, refer to the AD9371 User Guide). In this interoperability report, only the main ADC datapath has been considered.
    Figure 4. TES configuration tab
  5. Set the Configurations based on the requirements and move to JESD204b setup tab, which appears as shown in Figure 5.
  6. In this tab, set the required JESD link parameters and lane rate for both Tx Deframer (DAC) and Rx Framer (Main ADC).
    Figure 5. JESD204B setup tab
  7. After configuring the GUI with required settings, the C scripts for configuring the EVM can be generated by clicking on Tools -> Create Script -> C script as shown in Figure 6. Save the file with name “myk_config” so that the existing software makefiles can be used for compiling the scripts.
    Figure 6. Generating configuration C scripts
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