AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

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ID 683183
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report x
Hardware Requirements Hardware Setup AD9371 EVM Software Setup Hardware Checkout Methodology for JESD204B Transmitter JESD204B IP Core and DAC Configurations Hardware Checkout Methodology for JESD204B Receiver JESD204B IP Core and Main ADC Configurations Deterministic Latency (Subclass 1) Test Results Test Result Comments Document Revision History for AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Hardware Checkout Methodology for JESD204B Transmitter x
Transmitter Data Link Layer Transmitter Transport Layer Scrambling
Transmitter Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Hardware Checkout Methodology for JESD204B Receiver x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

Initial Frame and Lane Synchronization

Table 7.  Initial Frame and Lane Synchronization Test Cases
Test Case Objective Description Passing Criteria

RX_ILA.1

 Check whether the initial frame synchronization state machine enters FS_DATA state upon receiving non /K/ characters.
The following signals in <ip_variant_name>_inst_phy.v are tapped:
  • jesd204_rx_pcs_data[(L*32)-1:0]
  • jesd204_rx_pcs_data_valid[L-1:0]
  • jesd204_rx_pcs_kchar_data[(L*4)-1:0] 9
The following signals in <ip_variant_name>.v are tapped:
  • rx_dev_sync_n
  • jesd204_rx_int

The rxlink_clk is used as the sampling clock for the Signal Tap.

Each lane is represented by 32-bit data bus in jesd204_rx_pcs_data. The 32-bit data bus for is divided into 4 octets.

  • /R/ character or K28.0 (0x1C) is observed after /K/ character at the jesd204_rx_pcs_data bus.
  • The jesd204_rx_pcs_data_valid signal must be asserted to indicate that data from the PCS is valid.
  • The rx_dev_sync_n and jesd204_rx_int signals are deasserted.
  • Each multiframe in ILAS phase ends with /A/ character K28.3 (0x7C).
  • The jesd204_rx_pcs_kchar_data signal is asserted whenever control characters like /K/, /R/, /Q/, or /A/ are observed.

RX_ILA.2

 Check the JESD204B configuration parameters from ADC in second multiframe.
The following signals in <ip_variant_name>_inst_phy.v are tapped:
  • jesd204_rx_pcs_data[(L*32)-1:0]
  • jesd204_rx_pcs_data_valid[L-1:0] 9
The following signal in <ip_variant_name>.v is tapped:
  • jesd204_rx_int

The rxlink_clk is used as the sampling clock for the Signal Tap.

The Nios console accesses the following registers:
  • ilas_octet0
  • ilas_octet1
  • ilas_octet2
  • ilas_octet3

The content of 14 configuration octets in second multiframe is stored in these 32-bit registers - ilas_octet0, ilas_octet1, ilas_octet2 and ilas_octet3.

  • /R/ character is followed by /Q/ character or K28.4 (0x9C) at the beginning of second multiframe.
  • The jesd204_rx_int is deasserted if there is no error.
  • Octets 0-13 read from these registers match with the JESD204B parameters in each test setup.

RX_ILA.3

 Check the lane alignment
The following signals in <ip_variant_name>_inst_phy.v are tapped:
  • jesd204_rx_pcs_data[(L*32)-1:0]
  • jesd204_rx_pcs_data_valid[L-1:0]9
The following signals in <ip_variant_name>.v are tapped:
  • rx_somf[3:0]
  • dev_lane_aligned
  • jesd204_rx_int

The rxlink_clk is used as the sampling clock for the Signal Tap.

  • The dev_lane_aligned is asserted upon the last /A/ character of the ILAS is received, which is followed by the first data octet.
  • The rx_somf marks the start of multiframe in user data phase.
  • The jesd204_rx_int is deasserted if there is no error.
9 L is the number of lanes.
Level Two Title