AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

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ID 683183
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report x
Hardware Requirements Hardware Setup AD9371 EVM Software Setup Hardware Checkout Methodology for JESD204B Transmitter JESD204B IP Core and DAC Configurations Hardware Checkout Methodology for JESD204B Receiver JESD204B IP Core and Main ADC Configurations Deterministic Latency (Subclass 1) Test Results Test Result Comments Document Revision History for AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Hardware Checkout Methodology for JESD204B Transmitter x
Transmitter Data Link Layer Transmitter Transport Layer Scrambling
Transmitter Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Hardware Checkout Methodology for JESD204B Receiver x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

Document Revision History for AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

Date Version Changes
December 2017 2017.12.18
  • Renamed the document as AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report.
  • Added a note to clarify that the IOPLL input reference clock is sourcing from device clock through global clock network in the Hardware Setup topic.
  • Updated for latest branding standards.
  • Made editorial updates throughout the document.
May 2017 2017.05.08 Initial release.
Level Two Title