AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

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ID 683183
Date 12/18/2017
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Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report x
Hardware Requirements Hardware Setup AD9371 EVM Software Setup Hardware Checkout Methodology for JESD204B Transmitter JESD204B IP Core and DAC Configurations Hardware Checkout Methodology for JESD204B Receiver JESD204B IP Core and Main ADC Configurations Deterministic Latency (Subclass 1) Test Results Test Result Comments Document Revision History for AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Hardware Checkout Methodology for JESD204B Transmitter x
Transmitter Data Link Layer Transmitter Transport Layer Scrambling
Transmitter Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Hardware Checkout Methodology for JESD204B Receiver x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

Hardware Setup

An Intel® Arria® 10 GX Development Kit is used with the ADI AD9371 daughter card module installed to the FMC connector A of the development board.

  • The AD9371 EVM derives power from FMC pins.
  • The clock generator AD9528 is available on the EVM. The reference clock for AD9528 is sourced from external clock.
  • The device clocks for both converter and FPGA are generated by AD9528.
  • The FPGA device clock is supplied through FMC pins. The link and frame clocks are generated from this device clock using Intel IOPLL.
  • For subclass 1, AD9528 clock generator on the EVM generates SYSREF for both FPGA and AD9371. The sysref for FPGA is supplied through FMC pins.
  • The sync_n signal is transmitted from
    • the DAC of AD9371 to FPGA through FMC.
    • the FPGA to ADC of AD9371 through FMC.
Figure 1. Hardware Setup

The following system-level diagram shows how the different modules connect in this design.

Figure 2. System Diagram
Note: The IOPLL input reference clock is sourcing from device clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network might introduce additional jitter to the IOPLL and transceiver PLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design.

In this setup, the maximum data rate of transceiver lanes is 6.144Gbps. The clock generator available on the EVM is used for clocking both the EVM and the FPGA. The SPI master in FPGA programs both AD9371 registers and AD9528 clock generator registers available on the EVM through 4 wire SPI interface via FMC pins. The reference clock for this clock generator has to be provided by an external clock source. The converter device clock, FPGA device clock, and SYSREF (for both FPGA and converters) are generated by AD9528. FPGA receives these clocks through FMC pins. The converters operate in a single JESD link in all configurations with a maximum of 4 lanes.

Level Two Title