AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

Download PDF
ID 683183
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report x
Hardware Requirements Hardware Setup AD9371 EVM Software Setup Hardware Checkout Methodology for JESD204B Transmitter JESD204B IP Core and DAC Configurations Hardware Checkout Methodology for JESD204B Receiver JESD204B IP Core and Main ADC Configurations Deterministic Latency (Subclass 1) Test Results Test Result Comments Document Revision History for AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Hardware Checkout Methodology for JESD204B Transmitter x
Transmitter Data Link Layer Transmitter Transport Layer Scrambling
Transmitter Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Hardware Checkout Methodology for JESD204B Receiver x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

JESD204B IP Core and DAC Configurations

The JESD204B IP Core parameters (L, M, and F) in this hardware checkout are natively supported by the AD9371 device's configuration registers. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD9371 operating conditions.

The hardware checkout testing implements the JESD204B IP Core with the following parameter configuration.

Table 5.  Parameter Configuration

Configuration

Mode

Mode

Mode

Mode

Mode

Mode

LMF

124

222

421

148

244

442

HD

0

0

1

0

0

0

S

1

1

1

1

1

1

N

16

16

16

16

16

16

N’

16

16

16

16

16

16

CS

0

0

0

0

0

0

CF

0

0

0

0

0

0

Subclass

1

1

1

1

1

1

Lane Rate (Gbps)

6.144

6.144

3.072

6.144

6.144

6.144

DAC IQ rate (MSPS)

153.6

307.2

307.2

76.8

153.6

307.2

AD9371 Device Clock (MHz)

153.6

153.6

153.6

153.6

153.6

153.6

FPGA Device Clock (MHz) 4

153.6

153.6

153.6

153.6

153.6

153.6

FPGA Management Clock (MHz)

100

100

100

100

100

100

FPGA Frame Clock (MHz) 5

153.6

307.2

76.8

76.8

153.6

153.6

FPGA Link Clock (MHz) 5

153.6

153.6

76.8

153.6

153.6

153.6

DAC RF local oscillator frequency (GHz)

1.0

1.0

1.0

1.0

1.0

1.0

Character Replacement

Enabled

Enabled

Enabled

Enabled

Enabled

Enabled

PCS Option

Hard PCS

Hard PCS

Hard PCS

Hard PCS

Hard PCS

Hard PCS

Data Pattern

Sine 6

Single pulse 7

Sinc 7

Sine 6

Single pulse 7

Sinc 7

Sine 6

Single pulse 7

Sinc 7

Sine 6

Single pulse 7

Sinc 7

Sine 6

Single pulse 7

Sinc 7

Sine 6

Single pulse 7

Sinc 7

4 The device clock is used to clock the transceiver.
5 The frame clock and link clock are derived from the device clock using an internal PLL.
6 Sine wave pattern is used in TX_TL.1 and TX_SCR.1 test cases to verify that pattern generated in the FPGA transport layer is transmitted by DAC analog channel.
7 Single pulse and sinc patterns are used in deterministic latency measurement test cases DL.3 and DL.4 only.
Level Two Title