Deterministic Latency (Subclass 1)
The figure below shows a block diagram of the deterministic latency test setup. AD9528 clock generator on the EVM provides periodic SYSREF pulses for both the AD9371 and JESD204B IP Core. The period of SYSREF pulses is configured to be an integer multiple of Local Multi Frame Clocks (LMFC). The SYSREF pulse restarts the LMF counter and realigns it to the LMFC boundary.
The link latency for DAC and ADC is measured collectively by performing external loopback at RF level using SMA cable. The time difference between rising edge of pattern transmitted at transmitter transport layer and rising edge of pattern received back at receiver transport layer gives us the link latency. This latency has to remain constant across multiple power cycles of the system.
While performing the loopback delay measurement, the transmitter and receiver are both configured with same JESD204B configurations. The only exception is the JESD204B receiver mode with LMF = 421, which cannot be implemented in Intel® Arria® 10 FPGA because of unsupported data rate. In this mode, the ADC and FPGA are configured with LMF=222 configuration and the data rate is 3.072 Gbps. The FPGA and DAC JESD transmitter are configured with LMF = 421 configuration and the data rate is 3.072 Gbps. This enables us to perform delay measurement for this mode.
Figure 9. Deterministic Latency Test Setup
The FPGA can generate a 16-bit digital sample for single pulse or sinc pattern at the transport layer. Either waveform can be used to measure the loopback latency. The transmitted pulse and received pulse are both plotted in Signal Tap Logic Analyzer. The time difference between the 2 pulses gives us the loopback latency which includes both transmitter link latency and receiver link latency.
| Test Case |
Objective |
Description |
Passing Criteria |
|---|---|---|---|
| DL.1 |
Check the FPGA SYSREF single detection. |
Check that the FPGA detects the first rising edge of SYSREF pulse. Read the status of sysref_singledet (bit[2]) identifier in syncn_sysref_ctrl register at address 0x54. |
The value of sysref_singledet identifier should be zero. |
| DL.2 |
Check the SYSREF capture. |
Check that FPGA and ADC capture SYSREF correctly and restart the LMF counter. Both FPGA and ADC are also repetitively reset. Read the value of rbd_count (bit[10:3]) identifier in rx_status0 register at address 0x80. |
If the SYSREF is captured correctly and the LMF counter restarts, for every reset, the rbd_count value should only drift a little due to word alignment. |
| DL.3 |
Measure the total latency. |
Measure the time difference between the rising edge of pulses in Signal Tap Logic Analyzer. |
The latency should be consistent. |
| DL.4 |
Re-measure the total latency after setup power cycle and FPGA reconfiguration. |
Measure the time difference between the rising edge of pulses in Signal Tap Logic Analyzer. |
The latency should be consistent. |