AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

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ID 683183
Date 12/18/2017
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Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report x
Hardware Requirements Hardware Setup AD9371 EVM Software Setup Hardware Checkout Methodology for JESD204B Transmitter JESD204B IP Core and DAC Configurations Hardware Checkout Methodology for JESD204B Receiver JESD204B IP Core and Main ADC Configurations Deterministic Latency (Subclass 1) Test Results Test Result Comments Document Revision History for AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Hardware Checkout Methodology for JESD204B Transmitter x
Transmitter Data Link Layer Transmitter Transport Layer Scrambling
Transmitter Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Hardware Checkout Methodology for JESD204B Receiver x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

Receiver Transport Layer

To check the data integrity of the payload data stream through the JESD204B receiver IP Core and transport layer, the ADC is fed with a monotone sine wave test data pattern. The ADC is also set to operate with the same configuration as set in the JESD204B IP Core.

The AD9371 downconverts from RF frequency to monotone frequency. This RF frequency is tunable by the user and specified to AD9371 as LO frequency. Depending on the required phase of I and Q streams, the input frequency at ADC analog channels should be LO frequency ± monotone frequency. In our configuration the input frequency of LO frequency – monotone frequency is used. This is easily available at AD9371 DAC analog output and the same waveform is looped back to ADC through SMA cable.

Figure 8. Data Integrity Check Using Sine WaveThe following figure shows the conceptual test setup for data integrity checking.
Table 8.  Transport Layer Test Cases
Test Case Objective Description Passing Criteria

RX_TL.1

Check the transport layer mapping using Sine test pattern.
The following signals in altera_jesd204_transport_rx_top.sv are tapped:
  • jesd204_rx_data_valid
The following signals in jesd204b_ed.sv are tapped:
  • data_error
  • jesd204_rx_int

The rxframe_clk is used as the sampling clock for the Signal Tap II.

  • The jesd204_rx_data_valid signal is asserted.
  • The jesd204_rx_int signals are deasserted.
  • Monotone sine wave with frequency same as that of transmitted monotone is observed in Signal Tap II when DAC analog output is looped back to ADC analog input.
Level Two Title