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1.3.2.1. Using Simulation Signal Activity Data in Power Analysis
1.3.2.2. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation
1.3.2.3. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities
1.3.2.4. Signal Activities from User Defaults Only
1.5.1. Complete Design Simulation Power Analysis Flow
1.5.2. Modular Design Simulation Power Analysis Flow
1.5.3. Multiple Simulation Power Analysis Flow
1.5.4. Overlapping Simulation Power Analysis Flow
1.5.5. Partial Design Simulation Power Analysis Flow
1.5.6. Vectorless Estimation Power Analysis Flow
2.4.1. Clock Power Management
2.4.2. Pipelining and Retiming
2.4.3. Architectural Optimization
2.4.4. I/O Power Guidelines
2.4.5. Dynamically Controlled On-Chip Terminations (OCT)
2.4.6. Memory Optimization (M20K/MLAB)
2.4.7. DDR Memory Controller Settings
2.4.8. DSP Implementation
2.4.9. Reducing High-Speed Tile (HST) Usage
2.4.10. Unused Transceiver Channels
2.4.11. Periphery Power reduction XCVR Settings
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1.7. Power Analysis Revision History
The following revision history applies to this chapter:
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2022.06.22 | 21.4 | In the Power Analysis Tools topic, added statements about Intel® Quartus® Prime Power Analyzer accuracy for Intel® Stratix® 10 and Intel® Agilex™ designs. |
2021.12.13 | 21.4 |
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2021.10.04 | 21.3 | Recast the note in the Power Analysis Tools topic for greater clarity. |
2021.03.29 | 21.1 |
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2020.12.07 | 20.3.0 | Added note to the Specifying the Default Toggle Rate topic. |
2020.10.05 | 20.3.0 |
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2020.04.13 | 20.1.0 | Added information about the Intel® FPGA Power and Thermal Calculator to the following topics:
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2019.12.04 | 19.1.0 |
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2019.08.02 | 19.1.0 |
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2019.07.03 | 19.1.0 |
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2019.04.01 | 19.1.0 |
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2018.09.24 | 18.1.0 |
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2018.06.11 | 18.0.0 |
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2017.05.08 | 17.0.0 | Removed references to PowerPlay name. Power analysis occurs in the Intel Quartus Prime Power Analyzer. |
2016.10.31 | 16.1.0 |
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2015.11.02 | 15.1.0 | Changed instances of Quartus II to Intel Quartus Prime. |
2014.12.15 | 14.1.0 |
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2014.08.18 | 14.0a10.0 | Updated "Current Drawn from Voltage Supplies" to clarify that for SoC devices or for Arria V SoC and Cyclone V SoC devices, there is no standalone ICC_AUX_SHARED current drawn information. The ICC_AUX_SHARED is reported together with ICC_AUX. |
November 2012 | 12.1.0 |
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June 2012 | 12.0.0 |
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November 2011 | 10.1.1 |
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December 2010 | 10.1.0 |
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July 2010 | 10.0.0 |
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November 2009 | 9.1.0 |
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March 2009 | 9.0.0 |
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November 2008 | 8.1.0 |
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May 2008 | 8.0.0 |
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