Visible to Intel only — GUID: mwh1410384065660
Ixiasoft
Visible to Intel only — GUID: mwh1410384065660
Ixiasoft
1.5.4. Overlapping Simulation Power Analysis Flow
You can perform a simulation on the entire design, and more exhaustive simulations on a submodule, such as 8b10b_rxerr. The following table lists the import specification for overlapping simulations:
File Name | Entity |
---|---|
full_design.vcd | Top |
error_cases.vcd | Top|8b10b_rxerr:err1 |
In this case, the software uses signal activities from error_cases.vcd for all the nodes in the generated .vcd and uses signal activities from full_design.vcd for only those nodes that do not overlap with nodes in error_cases.vcd. In general, the more specific hierarchy (the most bottom-level module) derives signal activities for overlapping nodes.