25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

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ID 683154
Date 9/15/2021
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Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives 10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. 25G Ethernet Intel FPGA IP Core Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the Intel® Stratix® 10 IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.4. Placement Settings for the 25G Ethernet Intel FPGA IP Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. TX RS-FEC 4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.5. Link Fault Signaling Interface 4.1.6. 25 GbE RX PCS 4.1.7. RX RS-FEC 4.1.8. Flow Control 4.1.9. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.4.1. IP Core Preamble Processing 4.1.4.2. IP Core Malformed Packet Handling 4.1.4.3. Length/Type Field Processing 4.1.4.4. RX CRC Checking and Dynamic Forwarding
4.1.4.3. Length/Type Field Processing x
4.1.4.3.1. Length Checking
4.1.8. Flow Control x
4.1.8.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.8.2. XON/XOFF Pause Frames
4.1.9. 1588 Precision Time Protocol Interfaces x
4.1.9.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.9.2. PTP Transmit Functionality 4.1.9.3. PTP Receive Functionality 4.1.9.4. External Time-of-Day Module for 1588 PTP Variations 4.1.9.5. PTP Timestamp and TOD Formats 4.1.9.6. Design Considerations in PTP
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. PHY Interface Signals 6.7. 1588 PTP Interface Signals 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals
6.4. Transceiver Reconfiguration Signals x
6.4.1. Accessing the Native PHY Registers in H-Tile Devices 6.4.2. Accessing the Native PHY Registers in L-Tile Devices
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives
10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

6.2. RX MAC Interface to User Logic

The RX MAC provides an Avalon® streaming interface to the FPGA fabric. The datapath consists of a single 64-bit word.
Table 16.   Avalon® Streaming RX Datapath All interface signals are clocked by the clk_rxmac clock.

Signal

Direction

Description

clk_rxmac Output Clock for the RX MAC. Recovered from the incoming data. This clock is guaranteed stable when rx_pcs_ready is asserted. The frequency of this clock is 390.625 MHz for 25G data rate and 156.25 MHz for 10G data rate.. All RX MAC interface signals are synchronous to clk_rxmac .
l1_rx_data[63:0] Output

Data output from the MAC. Bit[63] is the MSB and bit[0] is the LSB. Bytes are read in the usual left to right order. The IP core reverses the byte order to meet the requirements of the Ethernet standard.

l1_rx_valid Output When asserted, indicates that l1_rx_data[63:0] is driving valid data.

If you turn off Enable RS-FEC , the IP core asserts this signal continuously between the assertions of l1_tx_startofpacket and l1_tx_endofpacket for the same packet. However, if you turn on Enable RS-FEC , the IP core drives IDLE cycles during alignment marker cycles.

l1_rx_startofpacket Output

When asserted, indicates the first byte of a frame.

l1_rx_endofpacket Output When asserted, indicates the last data byte of a frame, before the frame check sequence (FCS). In CRC pass-through mode, it is the last byte of the FCS. The packet can end at any byte position.
l1_rx_empty[2:0] Output Specifies the number of empty bytes when l1_rx_endofpacket is asserted.

The packet can end at any byte position. The empty bytes are the low-order bytes.

l1_rx_error[5:0] Output

When asserted in the same cycle as l1_rx_endofpacket, indicates the current packet should be treated as an error packet. The 6 bits of l1_rx_error specify the following errors:

  • l1_rx_error[5]: Unused.
  • l1_rx_error[4]: Payload length error. If the length field is <1535 bytes (0x600 bytes), the received payload length is less than what is advertised in the payload length field.
  • l1_rx_error[3]: Oversized frame. The frame size is greater than the value specified in the MAX_RX_SIZE_CONFIG register.
  • l1_rx_error[2]: Undersized frame – The frame size is less than 64 bytes. Frame size = header size + payload size.
  • l1_rx_error[1]: CRC Error. The computed CRC value differs from the received CRC.
  • l1_rx_error[0]: Malformed packet. The packet is terminated with a non-terminate control character. When this bit is asserted, l1_rx_error[1] is also asserted.
l1_rxstatus_valid Output When asserted, indicates that l1_rxstatus_data is driving valid data.
l1_rxstatus_data[39:0] Output

Specifies information about the received frame. The following fields are defined:

  • Bit[39]: When asserted, indicates a PFC frame
  • Bit[38]: When asserted, indicates a unicast frame
  • Bit[37]: When asserted, indicates a multicast frame
  • Bit[36]: When asserted, indicates a broadcast frame
  • Bit[35]: When asserted, indicates a pause frame
  • Bit[34]: When asserted, indicates a control frame
  • Bit[33]: When asserted, indicates a VLAN frame
  • Bit[32]: When asserted, indicates a stacked VLAN frame
  • Bits[31:16]: Specifies the frame length from the first byte of the destination address to the last bye of the FCS
  • Bits[15:0]: Specifies the payload length
pause_receive_rx[FCQN-1:0] Output Each bit of pause_receive_rx[FCQN-1:0] indicates that the corresponding queue is being paused.
Figure 36.  25G Ethernet Intel FPGA IP MAC to Client Avalon® Streaming Interface l1_rx_data reception order is highest byte to lowest byte. The first byte of the destination address is on l1_rx_data[65:56] , 0xfbe4 . . . in this timing diagram.
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