25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public

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6.4.2. Accessing the Native PHY Registers in L-Tile Devices

All variants of Intel® Stratix® 10 L-tile devices (ES and production) do not have background calibration. If the Enable auto adaptation triggering for RX PMA CTLE/DFE mode option is enabled, the auto adaptation module FSM needs to be held in IDLE state prior to accessing the transceiver core reconfiguration register. If the Enable auto adaptation triggering for RX PMA CTLE/DFE mode option is disabled, skip the steps below.

In Intel® Quartus® Prime software version 20.2 onwards, follow these steps to access the transceiver core reconfiguration registers:

  1. Write 0x1 into register 0x343[0] of the memory-mapped control and status interface to hold the auto adaptation module in an idle state.
  2. Access the transceiver register, for example, to perform the transceiver reconfiguration.
  3. Once completed, write 0x0 into register 0x343[0] of the Avalon® memory-mapped control and status interface to release the auto adaptation module.
Note: If you do not select the Enable auto adaptation triggering for RX PMA CTLE/DFE mode parameter, refer to Adaptation Control - Start section of the L- and H-Tile Transceiver PHY User Guide for more information about how to start adaptation.