25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

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ID 683154
Date 9/15/2021
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Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives 10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. 25G Ethernet Intel FPGA IP Core Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the Intel® Stratix® 10 IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.4. Placement Settings for the 25G Ethernet Intel FPGA IP Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. TX RS-FEC 4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.5. Link Fault Signaling Interface 4.1.6. 25 GbE RX PCS 4.1.7. RX RS-FEC 4.1.8. Flow Control 4.1.9. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.4.1. IP Core Preamble Processing 4.1.4.2. IP Core Malformed Packet Handling 4.1.4.3. Length/Type Field Processing 4.1.4.4. RX CRC Checking and Dynamic Forwarding
4.1.4.3. Length/Type Field Processing x
4.1.4.3.1. Length Checking
4.1.8. Flow Control x
4.1.8.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.8.2. XON/XOFF Pause Frames
4.1.9. 1588 Precision Time Protocol Interfaces x
4.1.9.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.9.2. PTP Transmit Functionality 4.1.9.3. PTP Receive Functionality 4.1.9.4. External Time-of-Day Module for 1588 PTP Variations 4.1.9.5. PTP Timestamp and TOD Formats 4.1.9.6. Design Considerations in PTP
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. PHY Interface Signals 6.7. 1588 PTP Interface Signals 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals
6.4. Transceiver Reconfiguration Signals x
6.4.1. Accessing the Native PHY Registers in H-Tile Devices 6.4.2. Accessing the Native PHY Registers in L-Tile Devices
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives
10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

6.6. PHY Interface Signals

Table 20.  Signals of the PHY InterfaceThis table lists the PHY interface signals. These interface signals are only applicable to the 25G Ethernet Intel FPGA IP with MAC and PCS core variant. For more information on these interface signals, refer to the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide.
Signal Direction Description
tx_clkout Input

When you turn on Enable IEEE 1588, this clock is a TX transceiver parallel clock. The frequency of this clock is 402.832 MHz for 25G data rate and 161.132 MHz for 10G rate.

When Enable IEEE 1588 is turned off, this clock is used by the MAC transmitter (TX MAC). The frequency of this clock is 390.625 MHz for 25G data rate and 156.25 MHz for 10G data rate.

tx_clkout2 Input Clock for the TX MAC when you turn on Enable IEEE 1588. The frequency of this clock is 390.625 MHz for 25G data rate and 156.25 MHz for 10G data rate.

This port is unused when Enable IEEE 1588 is turned off.

rx_clkout Input

When you turn on Enable IEEE 1588, this clock is a RX transceiver parallel clock. The frequency of this clock is 402.832 MHz for 25G data rate and 161.132 MHz for 10G rate.

When Enable IEEE 1588 is turned off, this clock is used by the MAC receiver (RX MAC). The frequency of this clock is 390.625 MHz for 25G data rate and 156.25 MHz for 10G data rate.

rx_clkout2 Input Clock for the RX MAC when you turn on Enable IEEE 1588. The frequency of this clock is 390.625 MHz for 25G data rate and 156.25 MHz for 10G data rate.

This port is unused when Enable IEEE 1588 is turned off.

rvalid Input Indication for RX valid data.
tvalid_phy Output Indicates valid data output towards PHY.
tx_parallel_data_phy[63:0] Output TX parallel data output from the FPGA fabric to PHY.
tx_control_phy[1:0] Output TX control character output from the FPGA fabric to PHY.

When you turn on Enable RS-FEC, the tx_control_phy does not transmit the control character to link partner. The 66-bits output from the RS-FEC is split into tx_parallel_data_phy[63:0] and tx_control_phy[1:0], where the tx_control_phy[1:0] is the most upper 2-bits of the 66-bits data bus, for example, {tx_control_phy[1:0], tx_parallel_data_phy[63:0]}.

For details about the TX RS-FEC, refer to the TX RS-FEC section.

rx_parallel_data_phy[63:0] Input RX parallel data input from the PHY to FPGA fabric.
rx_control_phy[1:0] Input RX control character input from the PHY to FPGA fabric.

When you turn on Enable RS-FEC, the rx_control_phy does not receive the control character from link partner. The 66-bits input to the RS-FEC is split into rx_parallel_data_phy[63:0] and rx_control_phy[1:0], where the rx_control_phy[1:0] is the most upper 2-bits of the 66-bits data bus, for example, {rx_control_phy[1:0], rx_parallel_data_phy[63:0]}.

For details about the RX RS-FEC, refer to the RX RS-FEC section.

tx_fifo_latency_pulse Input Latency pulse for TX Core FIFO.
tx_pcs_fifo_latency_pulse Input Latency pulse for TX PCS FIFO.
rx_fifo_latency_pulse Input Latency pulse for RX Core FIFO.
rx_pcs_fifo_latency_pulse Input Latency pulse for RX PCS FIFO.
rx_bitslip Output Indicates bit slip enable status.
rx_digitalreset Input Resets the PCS RX portion of the transceiver PHY.
tx_digitalrest Input Resets the PCS TX portion of the transceiver PHY.
rx_is_lockedtodata Input Indicates the status of RX CDR lock on data.
rx_set_locktoref Output Indicates the status of RX CDR lock to reference clock.
rx_seriallpbken Output Status for Internal Serial Loopback.
tx_ready Input Indication for external PMA TX Ready.
rx_ready Input Indication for external PMA RX Ready
phy_reset Output Reset signal for PHY.
tx_empty_phy Input Indication for TX Core FIFO empty.
tx_pempty_phy Input Indication for TX Core FIFO partially empty.
tx_full_phy Input Indication for TX Core FIFO full.
tx_pfull_phy Input Indication for TX Core FIFO partially full.
rx_empty_phy Input Indication for RX Core FIFO empty.
rx_pempty_phy Input Indication for RX Core FIFO partially empty.
rx_full_phy Input Indication for RX Core FIFO full.
rx_pfull_phy Input Indication for RX Core FIFO partially full.
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