25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

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ID 683154
Date 9/15/2021
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Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives 10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. 25G Ethernet Intel FPGA IP Core Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the Intel® Stratix® 10 IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.4. Placement Settings for the 25G Ethernet Intel FPGA IP Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. TX RS-FEC 4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.5. Link Fault Signaling Interface 4.1.6. 25 GbE RX PCS 4.1.7. RX RS-FEC 4.1.8. Flow Control 4.1.9. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.4.1. IP Core Preamble Processing 4.1.4.2. IP Core Malformed Packet Handling 4.1.4.3. Length/Type Field Processing 4.1.4.4. RX CRC Checking and Dynamic Forwarding
4.1.4.3. Length/Type Field Processing x
4.1.4.3.1. Length Checking
4.1.8. Flow Control x
4.1.8.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.8.2. XON/XOFF Pause Frames
4.1.9. 1588 Precision Time Protocol Interfaces x
4.1.9.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.9.2. PTP Transmit Functionality 4.1.9.3. PTP Receive Functionality 4.1.9.4. External Time-of-Day Module for 1588 PTP Variations 4.1.9.5. PTP Timestamp and TOD Formats 4.1.9.6. Design Considerations in PTP
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. PHY Interface Signals 6.7. 1588 PTP Interface Signals 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals
6.4. Transceiver Reconfiguration Signals x
6.4.1. Accessing the Native PHY Registers in H-Tile Devices 6.4.2. Accessing the Native PHY Registers in L-Tile Devices
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives
10. Document Revision History for the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

4.1.4.2. IP Core Malformed Packet Handling

While receiving an incoming packet from the Ethernet link, the 25G Ethernet Intel FPGA IP core expects to detect a terminate character at the end of the packet. When it detects an expected terminate character, the IP core generates an EOP on the client interface. However, sometimes the IP core detects an unexpected control character when it expects a terminate character.

If the 25G Ethernet Intel FPGA IP core detects an Error character, a Start character, an IDLE character, or any other non-terminate control character, when it expects a terminate character, it performs the following actions:

  • Generates an EOP.
  • Asserts a malformed packet error (l1_rx_error[0] ).
  • Asserts an FCS error (l1_rx_error[1] ).

If the IP core subsequently detects a terminate character, it does not generate another EOP indication.

When the IP core receives a packet that contains an error deliberately introduced on the Ethernet link using the 25G Ethernet Intel FPGA IP TX error insertion feature, the IP core identifies it as a malformed packet.

At this time, the 25G Ethernet Intel FPGA IP core does not recognize non-zero 4-bit ordered set types as an error.

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