25G Ethernet Intel® Stratix® 10 FPGA IP User Guide

ID 683154
Date 9/15/2021
Public

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6.8. Miscellaneous Status and Debug Signals

The miscellaneous status and debug signals are asynchronous.
Table 22.  Miscellaneous Status and Debug Signals

Signal

Direction

Description

tx_lanes_stable Output Asserted when all TX lanes are stable and ready to transmit data.
rx_block_lock Output

Signal is asserted when 64B/66B sync header is found consecutively for at least 64 clock cycles by the RX PCS.

rx_am_lock Output

If you turn on Enable RS-FEC in the parameter editor, this signal is asserted when alignment marker lock status is achieved.

If you turn off Enable RS-FEC in the parameter editor, this signal behaves the same as the rx_block_lock signal.

rx_pcs_ready Output

Signal is asserted when rx_block_lock is asserted.

local_fault_status Output Asserted when the RX MAC detects a local fault. This signal is available if you turn on Enable link fault generation in the parameter editor.
remote_fault_status Output Asserted when the RX MAC detects a remote fault. This signal is available if you turn on Enable link fault generation in the parameter editor.
unidirectional_en Output Asserted if the IP core includes Clause 66 for unidirectional support. This signal is available if you turn on Enable link fault generation in the parameter editor.
link_fault_gen_en Output Asserted if the IP core includes Clause 66 for unidirectional support. This signal is available if you turn on Enable link fault generation in the parameter editor.