GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone®...

GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

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ID 683136

Date 1/25/2022

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Document Table of Contents

Document Table of Contents x

GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x

Release Information for GPIO Intel® FPGA IP GPIO Intel® FPGA IP Features GPIO Intel® FPGA IP Data Paths GPIO Intel® FPGA IP Interface Signals Verifying Resource Utilization and Design Performance GPIO Intel® FPGA IP Parameter Settings Register Packing GPIO Intel® FPGA IP Timing GPIO Intel® FPGA IP Design Examples IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices GPIO Intel® FPGA IP User Guide Archives Document Revision History for GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

GPIO Intel® FPGA IP Data Paths x

Input Path Output and Output Enable Paths

GPIO Intel® FPGA IP Interface Signals x

Shared Signals Data Bit-Order for Data Interface Input and Output Bus High and Low Bits Data Interface Signals and Corresponding Clocks

GPIO Intel® FPGA IP Timing x

Timing Components Delay Elements Timing Analysis Timing Closure Guidelines

Timing Analysis x

Single Data Rate Input Register Full-Rate or Half-Rate DDIO Input Register Single Data Rate Output Register Full-Rate or Half-Rate DDIO Output Register

GPIO Intel® FPGA IP Design Examples x

GPIO IP Core Synthesizable Intel® Quartus® Prime Design Example GPIO IP Core Simulation Design Example

IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x

Migrating Your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP Cores Guideline: Swap datain_h and datain_l Ports in Migrated IP

GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Release Information for GPIO Intel® FPGA IP

GPIO Intel® FPGA IP Features

GPIO Intel® FPGA IP Data Paths

Input Path

Output and Output Enable Paths

GPIO Intel® FPGA IP Interface Signals

Shared Signals

Data Bit-Order for Data Interface

Input and Output Bus High and Low Bits

Data Interface Signals and Corresponding Clocks

Verifying Resource Utilization and Design Performance

GPIO Intel® FPGA IP Parameter Settings

GPIO Intel® FPGA IP Timing

Timing Components

Delay Elements

Timing Analysis

Single Data Rate Input Register

Full-Rate or Half-Rate DDIO Input Register

Single Data Rate Output Register

Full-Rate or Half-Rate DDIO Output Register

Timing Closure Guidelines

GPIO Intel® FPGA IP Design Examples

GPIO IP Core Synthesizable Intel® Quartus® Prime Design Example

GPIO IP Core Simulation Design Example

IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices

Migrating Your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP Cores

Guideline: Swap datain_h and datain_l Ports in Migrated IP

GPIO Intel® FPGA IP User Guide Archives

Document Revision History for GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

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GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Updated for:
Intel® Quartus® Prime Design Suite 21.4
IP Version 21.0.0

The GPIO Intel® FPGA IP core supports the general purpose I/O (GPIO) features and components. You can use GPIOs in general applications that are not specific to transceivers, memory interfaces, or LVDS.

The GPIO IP core is available for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices only. If you are migrating designs from Stratix® V, Arria® V, or Cyclone® V devices, you must migrate the ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, or ALTIOBUF IP cores.