GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

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ID 683136
Date 1/25/2022
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Document Table of Contents
Document Table of Contents x
GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Release Information for GPIO Intel® FPGA IP GPIO Intel® FPGA IP Features GPIO Intel® FPGA IP Data Paths GPIO Intel® FPGA IP Interface Signals Verifying Resource Utilization and Design Performance GPIO Intel® FPGA IP Parameter Settings Register Packing GPIO Intel® FPGA IP Timing GPIO Intel® FPGA IP Design Examples IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices GPIO Intel® FPGA IP User Guide Archives Document Revision History for GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
GPIO Intel® FPGA IP Data Paths x
Input Path Output and Output Enable Paths
GPIO Intel® FPGA IP Interface Signals x
Shared Signals Data Bit-Order for Data Interface Input and Output Bus High and Low Bits Data Interface Signals and Corresponding Clocks
GPIO Intel® FPGA IP Timing x
Timing Components Delay Elements Timing Analysis Timing Closure Guidelines
Timing Analysis x
Single Data Rate Input Register Full-Rate or Half-Rate DDIO Input Register Single Data Rate Output Register Full-Rate or Half-Rate DDIO Output Register
GPIO Intel® FPGA IP Design Examples x
GPIO IP Core Synthesizable Intel® Quartus® Prime Design Example GPIO IP Core Simulation Design Example
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP Cores Guideline: Swap datain_h and datain_l Ports in Migrated IP
GPIO Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

GPIO Intel® FPGA IP Parameter Settings

You can set the parameter settings for the GPIO IP core in the Intel® Quartus® Prime software. There are three groups of options: General, Buffer, and Registers.
Table 9.   GPIO IP Core Parameters - General
Parameter Condition Allowed Values Description
Data Direction —
  • Input
  • Output
  • Bidir

Specifies the data direction for the GPIO.
Data width —

1 to 128

Specifies the data width.

Use legacy top-level port names —
  • On
  • Off

Use same port names as in Stratix® V, Arria® V, and Cyclone® V devices.

For example, dout becomes dataout_h and dataout_l, and din becomes datain_h and datain_l.

Note: The behavior of these ports are different than in the Stratix® V, Arria® V, and Cyclone® V devices. For the migration guideline, refer to the related information.
Table 10.   GPIO IP Core Parameters - Buffer
Parameter Condition Allowed Values Description
Use differential buffer —
  • On
  • Off

If turned on, enables differential I/O buffers.
Use pseudo differential buffer
  • Data Direction = Output
  • Use differential buffer = On
  • On
  • Off

If turned on in output mode, enables pseudo differential output buffers.

This option is automatically turned on for bidirectional mode if you turn on Use differential buffer.

Use bus-hold circuitry
  • Data Direction = Input or Bidir
  • Use differential buffer = Off
  • On
  • Off

If turned on, the bus hold circuitry can weakly hold the signal on an I/O pin at its last-driven state where the output buffer state will be 1 or 0 but not high-impedance.

Use open drain output
  • Data Direction = Output or Bidir
  • Use differential buffer = Off
  • On
  • Off

If turned on, the open drain output enables the device to provide system-level control signals such as interrupt and write enable signals that can be asserted by multiple devices in your system.

Enable output enable port Data Direction = Output
  • On
  • Off

If turned on, enables user input to the OE port. This option is automatically turned on for bidirectional mode.

Enable seriestermination / paralleltermination ports —
  • On
  • Off

If turned on, enables the seriesterminationcontrol and parallelterminationcontrol ports of the output buffer.

Table 11.   GPIO IP Core Parameters - Registers
Parameter Condition Allowed Values Description
Register mode —
  • None
  • Simple register
  • DDIO
 Specifies the register mode for the GPIO IP core:
  • None—specifies a simple wire connection from/to the buffer.
  • Simple register—specifies that the DDIO is used as a simple register in single data-rate mode (SDR). The Fitter may pack this register in the I/O.
  • DDIO— specifies that the IP core uses the DDIO.
Enable synchronous clear / preset port
  • Register mode = DDIO
  • None
  • Clear
  • Preset

Specifies how to implement synchronous reset port.

  • None—Disables synchronous reset port.
  • Clear—Enables the SCLR port for synchronous clears.
  • Preset—Enables the SSET port for synchronous preset.
Enable asynchronous clear / preset port
  • Register mode = DDIO
  • None
  • Clear
  • Preset

Specifies how to implement asynchronous reset port.

  • None—Disables asynchronous reset port.
  • Clear—Enables the ACLR port for asynchronous clears.
  • Preset—Enables the ASET port for asynchronous preset.

ACLR and ASET signals are active high.

Enable clock enable ports Register mode = DDIO
  • On
  • Off
  • On—exposes the clock enable (CKE) port to allow you to control when data is clocked in or out. This signal prevents data from being passed through without your control.
  • Off—clock enable port is not exposed and data always pass through the register automatically.
Half Rate logic Register mode = DDIO
  • On
  • Off
 If turned on, enables half-rate DDIO.
Separate input / output Clocks
  • Data Direction = Bidir
  • Register mode = Simple register or DDIO
  • On
  • Off
 If turned on, enables separate clocks (CK_IN and CK_OUT) for the input and output paths in bidirectional mode.
Related Information
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