2023.09.13 |
23.2 |
21.0.0 |
- Updated the reset interface signals description to improve clarity.
- Updated the link to the topic about using the Intel Quartus Prime Timing Analyzer.
- Updated the IP migration guideline to specify that the GPIO IP drives datain_h on the falling edge and datain_l on the rising edge.
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2022.01.25 |
21.4 |
21.0.0 |
- Corrected the output clock name in the topic about the single data rate output register from sdr_out_clk to sdr_out_outclk.
- Updated the GPIO IP version number to 21.0.0.
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2021.07.15 |
21.2 |
20.0.0 |
Updated the diagram that shows the simplified view of the single-ended GPIO input path to update dout[0] to dout[3] and dout[3] to dout[0]. |
2021.03.29 |
21.1 |
20.0.0 |
Updated the GPIO IP version number to 20.0.0. |
2021.03.12 |
20.4 |
19.3.0 |
Updated the IP migration guideline to specify that the GPIO IP drives datain_h on the rising edge and datain_l on the falling edge. |
2019.10.01 |
19.3 |
19.3.0 |
Corrected typographical error in the .qsf assignment codes in the topic about delay elements. |
2019.03.04 |
18.1 |
18.1 |
In the topics about the input path, and output and output enable paths:
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2018.08.28 |
18.0 |
18.0 |
- Retitled the document from Intel FPGA GPIO IP Core User Guide to GPIO Intel FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices.
- Added a link to the Intel® Stratix® 10 GPIO IP user guide.
- Renamed the IP from "Intel FPGA GPIO" to "GPIO Intel FPGA IP".
- Corrected instances of "clk_fr" and "clk_hr" to "ck_fr" and "ck_hr".
- Updated the GPIO IP input path and output paths diagrams to show the actual IP core signal names.
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