Visible to Intel only — GUID: eis1415169054289
Ixiasoft
Visible to Intel only — GUID: eis1415169054289
Ixiasoft
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 17.0 |
The ALTDDIO Intel® FPGA IP configure the DDR I/O registers in APEX™ II, Arria® II, Arria® V, Cyclone® IV, Cyclone® V, Intel® Cyclone® 10 LP, HardCopy®, Stratix® IV, and Stratix® V devices.
You can also use these IP cores to implement DDR registers in the logic elements (LEs). In Arria® GX, Stratix® series, HardCopy II, HardCopy Stratix® , and APEX™ II devices, the DDR registers are implemented in the I/O element (IOE). In Cyclone® series devices, the IP cores automatically implement the DDR registers in the LEs closest to the pin. The ALTDDIO_IN IP core implements the interface for DDR inputs. The ALTDDIO_OUT IP core implements the interface for DDR outputs. The ALTDDIO_BIDIR Intel® FPGA IP implements the interface for bidirectional DDR inputs and outputs.