Visible to Intel only — GUID: prv1566295293772
Ixiasoft
1. Agilex™ 7 SEU Mitigation Overview
2. Agilex™ 7 CRAM Error Mitigation
3. Secure Device Manager ECC and SmartVID Errors Detection
4. Agilex™ 7 SEU Mitigation Implementation Guides
5. IP and Software References
6. Agilex™ 7 SEU Mitigation User Guide Archives
7. Document Revision History for the Agilex™ 7 SEU Mitigation User Guide
4.6.1. Launching and Setting Up the Fault Injection Debugger
4.6.2. Configuring Your Device using a Software Object File (.sof)
4.6.3. Constraining Regions for Fault Injection
4.6.4. Injecting Errors to Random Locations
4.6.5. Injecting Errors to Specific Locations
4.6.6. Injecting Double Adjacent Errors
4.6.7. Injecting SDM ECC Errors
4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
Visible to Intel only — GUID: prv1566295293772
Ixiasoft
2.4.1.4. Sensitivity Map Header Lookup
The .smh file represents a hash of the design's CRAM bit settings. The .smh file maps related groups of CRAM to a signal bit in the sensitivity array.
During an SEU, your application can look up the .smh file to determine if a bit is used. Using the bit location information, you can reduce the effective soft error rate in a running system.
The following criteria determine the criticality of a CRAM location in your design:
- Routing—all bits that control a utilized routing line are considered sensitive.
- Adaptive logic modules (ALMs)—if you configure an ALM, the Advanced SEU Detection IP considers all CRAM bits related to that ALM as sensitive.
- Logic array block (LAB) control lines—if you use an ALM in a LAB, the Advanced SEU Detection IP considers all bits related to the control signals feeding that LAB as sensitive.
- M20K memory and digital signal processing (DSP) blocks—if you use a block, the Advanced SEU Detection IP considers all CRAM bits related to that block as sensitive.