Agilex™ 7 SEU Mitigation User Guide

ID 683128
Date 9/20/2024
Public
Document Table of Contents

7. Document Revision History for the Agilex™ 7 SEU Mitigation User Guide

Document Version Quartus® Prime Version Changes
2024.09.20 23.3
  • Corrected the information about the scrubbing feature in the Setting Up the SEU Mitigation Features.
  • Added new Figure: Setting the SEU_ERROR Pin.
2024.02.20 23.3
  • Updated subsection: Error Message Queue to clarify that the SDM firmware may not capture the SEU error if the SEU error occurs within the sectors used for partial reconfiguration, from one SEU interval before the partial reconfiguration until the partial reconfiguration completion.
  • Updated subsection: Failure Rates.
2023.10.02 23.3
  • Updated subsection: Error Message Queue.
  • Added Table: SDM Miscellaneous Error Message Bit Description.
  • Updated footnote in Scrubbing section.
  • Updated examples of the quartus_fid command in Injecting Double Adjacent Errors: Command-Line Interface section.
  • Added information about seu_error_out port in Advanced SEU Detection IP Core Ports section:
    • Figure: Advanced SEU Detection IP Core On-Chip Sensitivity Processing Block Diagram
    • Table: Advanced SEU Detection IP Core On-Chip Sensitivity Processing Ports
    • Figure: Advanced SEU Detection IP Core Off-Chip Sensitivity Processing Block Diagram
    • Table: Advanced SEU Detection IP Core Off-Chip Sensitivity Processing Ports
  • Updated the following tables:
    • Error Message Queue Bit Description
    • SDM and Subsystem ECC Error Message Bits Description
    • SmartVID Error Message Bits Description
2023.04.10 23.1
  • Added link to Intel Agilex 7 FPGA and SoCs Device Overview in Memory Blocks section.
  • Updated link to Memory Blocks Error Correction Code Support, Intel Agilex 7 Embedded Memory User Guide in CRAM Error Detection and Correction and Memory Blocks sections.
  • Updated the 27:25 and 24:12 Bit in Table: Error Message Queue Bit Description.
  • Added Enable generic SDM error handling parameter in Table: Advanced SEU Detection IP Core Parameter Settings.
  • Updated information in Table: Advanced SEU Detection Intel FPGA IP Current Release Information.
  • Added information about configuring LUTRAM in Fault Injection Debugger section.
  • Added step to turn on LUTRAM Checking in Injecting Errors to Random Locations section.
  • Updated Figure: Fault Injection Debugger GUI and Table: Fault Injection Debugger GUI Control including descriptions of the LUTRAM Checking control.
  • Added arguments for lutram control in Fault Injection Debugger Command-Line Interface section.
2022.12.30 21.3
  • Added subsection: CRAM Error Detection and Correction.
  • Updated section: Scrubbing.
2022.09.26 21.3
  • Added note in Advanced SEU Detection IP Core.
  • Added note in Minimum SEU interval setting in Intel Quartus Prime SEU Software Settings.
  • Removed the footnote in Table: Advanced SEU Detection Intel® FPGA IP Core Current Release Information.
2021.10.28 21.3
  • Added information about the actual minimum SEU interval being higher than the value you specify.
  • Added support for SDM ECC and SmartVID errors detection.
  • Added steps to inject SDM ECC errors using the command line or the GUI.
  • Added steps to analyze SEU errors using Signal Tap.
2021.07.05 21.2 Updated the Advanced SEU Detection IP core ports.
2021.04.15 21.1
  • Added support for correction of double adjacent errors.
  • Added support for detection of multiple bit errors.
  • Added support for the Advanced SEU Detection Intel® FPGA IP, including IP parameter and ports references.
  • Added support for the Fault Injection Debugger tool, including descriptions of the GUI tool and command-line interface commands.
  • Updated the number of messages stored in the error message queue from four to eight.
  • Updated the topic about scrubbing to provide clarity about partial reconfiguration, uncorrectable error alerts, and scrubbing priority.
  • Updated the topic about setting up the SEU mitigation features to enable fault injection.
  • Added sections for:
    • SEU sensitivity processing, including on-chip and off-chip lookup.
    • Sensitivity map header programming, lookup, and Sensitivity Map Header Revision 4 file format.
    • Design hierarchy sensitivity classification, assignment, and tagging.
    • Evaluation of system response to upsets.
    • Constraining regions for fault injection.
    • Injecting errors to random or specific locations.
    • Injecting double adjacent errors.
    • Updated the off-chip sensitivity processing ports information of the Advanced SEU Detection IP.
2019.10.17 19.3 Initial release.