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1. Agilex™ 7 SEU Mitigation Overview
2. Agilex™ 7 CRAM Error Mitigation
3. Secure Device Manager ECC and SmartVID Errors Detection
4. Agilex™ 7 SEU Mitigation Implementation Guides
5. IP and Software References
6. Agilex™ 7 SEU Mitigation User Guide Archives
7. Document Revision History for the Agilex™ 7 SEU Mitigation User Guide
4.6.1. Launching and Setting Up the Fault Injection Debugger
4.6.2. Configuring Your Device using a Software Object File (.sof)
4.6.3. Constraining Regions for Fault Injection
4.6.4. Injecting Errors to Random Locations
4.6.5. Injecting Errors to Specific Locations
4.6.6. Injecting Double Adjacent Errors
4.6.7. Injecting SDM ECC Errors
4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
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5.1.2. Advanced SEU Detection Intel® FPGA IP Ports
Figure 18. Advanced SEU Detection Intel® FPGA IP On-Chip Sensitivity Processing Block Diagram
Ports | Width | Direction | Description |
---|---|---|---|
clk | 1 | Input | User input clock. The maximum frequency is 250 MHz. |
reset | 1 | Input | Active high, synchronous reset signal.
Note: For IP instantiation guidelines, refer to the related information about the Reset Release Intel® FPGA IP.
|
sys_error | 1 | Output | Logic high indicates that there is an error in the system while retrieving the SEU error. |
busy | 1 | Output | Logic high indicates that the Advanced SEU Detection Intel® FPGA IP is busy processing the SEU data. The signal goes low when processing completes with assertion of the critical_error or noncritical_error signal. |
generic_sdm_valid_out | 1 | Output | Logic high for one clock cycle indicates that the device detects an SDM and Subsystem ECC or SmartVID or Misc SDM or Misc CNT error. |
generic_sdm_data_out | 64 | Output | Outputs the SDM ECC and Subsystem ECC or SmartVID or Misc SDM or Misc CNT error message content. |
critical_clear | 1 | Input | Assert high to clear the error report (critical_error, noncritical_error, regions_report, and seu_data) for the last processed SEU data input. |
critical_error | 1 | Output | Logic high indicates that a.smh lookup determined that the SEU error is in a critical region. |
noncritical_error | 1 | Output | Logic high indicates that a .smh lookup determined that the SEU error is in a non-critical region. |
seu_data | 64 | Output | Shows the SEU error message for the last processed SEU data input. The port is available if you turn on Show raw SEU error message. For more information, refer to the related information about the error message queue. |
regions_report | 1–32 | Output | Indicates the region ID for the error as reported by the .smh lookup. The port width of this signal is set by the Largest ASD region ID used parameter. |
address | 32 | Output | Avalon® memory-mapped interface address bus in unit of Byte addressing. |
read | 1 | Output | Avalon® memory-mapped interface read control signal. |
waitrequest | 1 | Input | Avalon® memory-mapped interface wait request signal. |
readdata | 32 | Input | Avalon® memory-mapped interface data bus. |
readdatavalid | 1 | Input | Avalon® memory-mapped interface data valid signal. |
seu_error_out | 1 | Output | Signal is synchronous with the input clock of the IP. Assert high when it detects SEU. |
Figure 19. Advanced SEU Detection Intel® FPGA IP Off-Chip Sensitivity Processing Block Diagram
Ports | Width | Direction | Description |
---|---|---|---|
clk | 1 | Input | User input clock. The maximum frequency is 250 MHz. |
reset | 1 | Input | Active high, synchronous reset signal.
Note: For IP instantiation guidelines, refer to the related information about the Reset Release Intel® FPGA IP.
|
sys_error | 1 | Output | Logic high indicates that there is an error in the system while retrieving the SEU error. |
generic_sdm_valid_out | 1 | Output | Logic high for one clock cycle indicates that the device detects an SDM and Subsystem ECC or SmartVID or Misc SDM or Misc CNT error. |
generic_sdm_data_out | 64 | Output | Outputs the SDM ECC and Subsystem ECC or SmartVID or Misc SDM or Misc CNT error message content. |
data | 64 | Output | Avalon® streaming interface data signal that provides SEU error message from the FIFO entry. |
valid | 1 | Output | Avalon® streaming interface data valid signal that indicates the avst_seu_source_data signal contains valid data. |
ready | 1 | Input | Avalon® streaming interface ready signal. |
seu_error_out | 1 | Output | Signal is synchronous with the input clock of the IP. Assert high when it detects SEU. |