Agilex™ 7 SEU Mitigation User Guide

ID 683128
Date 9/20/2024
Public
Document Table of Contents

2.4.1.2. On-Chip Lookup Sensitivity Processing

For the on-chip sensitivity processing, the Advanced SEU Detection Intel® FPGA IP reads the error message queue content and then compares single-bit error locations with a sensitivity map. This check determines whether or not the failure affects the device operation.
Figure 4. System Overview for On-Chip Lookup Sensitivity Processing with Advanced SEU Detection Intel® FPGA IP


Figure 5. Process Flow for On-Chip Lookup Sensitivity Processing