Visible to Intel only — GUID: fui1503899520177
Ixiasoft
Visible to Intel only — GUID: fui1503899520177
Ixiasoft
5.1.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings
Parameters | Value | Default Value | Description |
---|---|---|---|
Use on-chip sensitivity processing |
|
On | Select to use external memory interface to access sensitivity data and perform SEU location look-up by the IP. |
Largest ASD region ID used | 1 to 32 | 1 | Specifies the largest ASD region ID used in the design. This option is available if you turn on Use on-chip sensitivity processing. The maximum number of region IDs classifications you can use in a design is 165. |
Sensitivity data start address | 0x0 | 0x0 | Specifies a constant offset to add to all addresses generated by the external memory interface. This option is available if you turn on Use on-chip sensitivity processing. |
Show raw SEU error message |
|
Off | Select to show raw SEU error message. This option is available if you turn on Use on-chip sensitivity processing. |
SEU error fifo depth |
|
4 | Specifies the number of SEU errors to store. |
Enable generic SDM error handling |
|
Off | Select to enable generic SDM error handling. |
Use with Fault Injection Debugger Tool |
|
Off | Turn on to use the IP with the Fault Injection Debugger tool. |
Export SEU_Error |
|
Off | Select to export SEU_ERROR as IP output signal, assert when SEU_ERROR detected. |