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1. Agilex™ 7 SEU Mitigation Overview
2. Agilex™ 7 CRAM Error Mitigation
3. Secure Device Manager ECC and SmartVID Errors Detection
4. Agilex™ 7 SEU Mitigation Implementation Guides
5. IP and Software References
6. Agilex™ 7 SEU Mitigation User Guide Archives
7. Document Revision History for the Agilex™ 7 SEU Mitigation User Guide
4.6.1. Launching and Setting Up the Fault Injection Debugger
4.6.2. Configuring Your Device using a Software Object File (.sof)
4.6.3. Constraining Regions for Fault Injection
4.6.4. Injecting Errors to Random Locations
4.6.5. Injecting Errors to Specific Locations
4.6.6. Injecting Double Adjacent Errors
4.6.7. Injecting SDM ECC Errors
4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
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2.4.1.2. On-Chip Lookup Sensitivity Processing
For the on-chip sensitivity processing, the Advanced SEU Detection Intel® FPGA IP reads the error message queue content and then compares single-bit error locations with a sensitivity map. This check determines whether or not the failure affects the device operation.
Figure 4. System Overview for On-Chip Lookup Sensitivity Processing with Advanced SEU Detection Intel® FPGA IP
Figure 5. Process Flow for On-Chip Lookup Sensitivity Processing