AN 780: Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL*

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ID 683045
Date 10/30/2018
Public
Document Table of Contents
Document Table of Contents x
1. Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL
1. Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL x
1.1. Introduction to Custom Platforms 1.2. OpenCL System Architecture 1.3. Hierarchical Structure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform's Hardware 1.4. Intel® Quartus® Prime Software Revisions Describing the Custom Platform 1.5. Intel® FPGA SDK for OpenCL™ and User Environment Setup 1.6. Intel® Arria® 10 Custom Platform Project Setup and Customization Procedure 1.7. Intel® Arria® 10 Custom Platform Customization Example 1.8. Updating Your Custom Platform to Target a Different Device 1.9. Migrating the Custom Platform between Different Intel® Quartus® Prime Software Versions 1.10. Document Revision History for Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL*
1.4. Intel® Quartus® Prime Software Revisions Describing the Custom Platform x
1.4.1. Descriptions of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Files
1.4.1. Descriptions of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Files x
1.4.1.1. Location of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform
1.5. Intel® FPGA SDK for OpenCL™ and User Environment Setup x
1.5.1. Specifying the Intel® FPGA SDK for OpenCL™ User Environment Variable Settings 1.5.2. Specifying the Intel® FPGA SDK for OpenCL™ User Environment Variables on Linux
1.5.1. Specifying the Intel® FPGA SDK for OpenCL™ User Environment Variable Settings x
1.5.1.1. Verifying the Windows Intel® FPGA SDK for OpenCL™ User Environment Variable Settings
1.5.2. Specifying the Intel® FPGA SDK for OpenCL™ User Environment Variables on Linux x
1.5.2.1. Verifying the Linux Intel® FPGA SDK for OpenCL™ User Environment Variable Settings
1.6. Intel® Arria® 10 Custom Platform Project Setup and Customization Procedure x
1.6.1. Custom Platform Versioning 1.6.2. Board XML Files 1.6.3. Customization Flow
1.6.2. Board XML Files x
1.6.2.1. The board_env.xml File 1.6.2.2. The board_spec.xml File
1.6.2.1. The board_env.xml File x
1.6.2.1.1. Creating the board_env.xml File
1.6.2.2. The board_spec.xml File x
1.6.2.2.1. Creating the board_spec.xml File
1.6.3. Customization Flow x
1.6.3.1. Compiling a Kernel without Regenerating the Custom Platform 1.6.3.2. Preparing an Existing Custom Platform for Customization
1.7. Intel® Arria® 10 Custom Platform Customization Example x
1.7.1. Modifying the board.qsys File in the Custom Platform 1.7.2. Modifying the Kernel (freeze_wrapper.v and board_spec.xml) 1.7.3. Updating the Top-Level I/O Ring with the Modified board.qsys and freeze_wrapper.v Files 1.7.4. Updating the Original Custom Platform Directory with the New Custom Platform Modifications 1.7.5. Compilation Log Files 1.7.6. Analyzing the Results from Compilation
1.7.1. Modifying the board.qsys File in the Custom Platform x
1.7.1.1. Opening an Existing Intel® Quartus® Prime Project and the board.qsys Platform Designer System Design 1.7.1.2. Adding the Avalon® -ST Single Clock FIFO Component into the Platform Designer System 1.7.1.3. Connecting the Avalon® -ST Single Clock FIFO Component's Exported Signals in the Top-Level Platform Designer System
1.7.2. Modifying the Kernel (freeze_wrapper.v and board_spec.xml) x
1.7.2.1. Opening an Existing Intel® Quartus® Prime Project and the kernel_system.qsys Platform Designer System Design 1.7.2.2. Adding an Avalon® -ST Adapter Component into the Platform Designer System 1.7.2.3. Connecting the Avalon® -ST Adapter Component's Exported Signals in the Top-Level Platform Designer System 1.7.2.4. Modifying the board_spec.xml File 1.7.2.5. Modifying the freeze_wrapper.v File
1.8. Updating Your Custom Platform to Target a Different Device x
1.8.1. Targeting a Device that Has a Migration Path in the Intel® Quartus® Prime Software 1.8.2. Targeting a Device that Has a Different Package Size
1.9. Migrating the Custom Platform between Different Intel® Quartus® Prime Software Versions x
1.9.1. Custom Platform Automigration for Forward Compatibility 1.9.2. Customizing Automigration 1.9.3. Overall Summary
1. Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL

1.7. Intel® Arria® 10 Custom Platform Customization Example

This section describes the process of modifying the a10gx_ref_18.1 Custom Platform that you prepared for customization.

Prerequisites for customization:

  • You have prepared the original Custom Platform for customization, as outlined in the Preparing an Existing Custom Platform for Customization section.
  • You have a <your kernel file name> directory within the Custom Platform directory. The vector_add directory mentioned herein was created after you compiled the a10gx_ref_18.1 Custom Platform for the first time using the Intel® FPGA SDK for OpenCL™ Offline Compiler, as described in the Compiling a Kernel without Regenerating the Custom Platform and Preparing an Existing Custom Platform for Customization sections.

The following information pertains to Steps 3 to 5 of the Customization Flow.

The figure below illustrates the customized a10gx_ref_18.1 Custom Platform’s hardware. Refer to Figure 2 for an illustration of the original Intel® Arria® 10 GX FPGA Development Kit Reference Platform’s architecture. Customization (shown in orange) includes adding an Avalon® Streaming ( Avalon® -ST) Single Clock FIFO component to the board.qsys file and then connecting it to the kernel via the freeze wrapper. Because the customization creates a streaming interface, you must alter the board_spec.xml file and change the channel property.

Figure 5. Architectural Representation of a Customized Custom Platform Based on the Intel® Arria® 10 GX FPGA Development Kit Reference Platform

Customizing the a10gx_ref_18.1 Custom Platform involves the following tasks:

  1. Modifying the board.qsys File in the Custom Platform
    Modify the board.qsys file by adding an Avalon® -ST Single Clock FIFO component.
  2. Modifying the Kernel (freeze_wrapper.v and board_spec.xml)
    Modify the freeze_wrapper.v and board_spec.xml files by adding an Avalon® -ST Adapter component.
  3. Updating the Top-Level I/O Ring with the Modified board.qsys and freeze_wrapper.v Files
    Add ports and signals to the board and freeze_wrapper instances in the top.v file.
  4. Updating the Original Custom Platform Directory with the New Custom Platform Modifications
    The final step to customizing your Custom Platform is to copy all modified files back into the original Custom Platform directory (that is, the a10gx_ref_18.1/hardware/a10gx_fifo directory).
  5. Compilation Log Files
    The compilation log files record verbose information while the software tools synthesize and compile the Custom Platform and the kernel.
  6. Analyzing the Results from Compilation
    After the full compilation flow has completed, check the results in the Intel® Quartus® Prime Pro Edition software GUI.
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