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1.1. Introduction to Custom Platforms
1.2. OpenCL System Architecture
1.3. Hierarchical Structure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform's Hardware
1.4. Intel® Quartus® Prime Software Revisions Describing the Custom Platform
1.5. Intel® FPGA SDK for OpenCL™ and User Environment Setup
1.6. Intel® Arria® 10 Custom Platform Project Setup and Customization Procedure
1.7. Intel® Arria® 10 Custom Platform Customization Example
1.8. Updating Your Custom Platform to Target a Different Device
1.9. Migrating the Custom Platform between Different Intel® Quartus® Prime Software Versions
1.10. Document Revision History for Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL*
1.7.1. Modifying the board.qsys File in the Custom Platform
1.7.2. Modifying the Kernel (freeze_wrapper.v and board_spec.xml)
1.7.3. Updating the Top-Level I/O Ring with the Modified board.qsys and freeze_wrapper.v Files
1.7.4. Updating the Original Custom Platform Directory with the New Custom Platform Modifications
1.7.5. Compilation Log Files
1.7.6. Analyzing the Results from Compilation
1.7.1.1. Opening an Existing Intel® Quartus® Prime Project and the board.qsys Platform Designer System Design
1.7.1.2. Adding the Avalon® -ST Single Clock FIFO Component into the Platform Designer System
1.7.1.3. Connecting the Avalon® -ST Single Clock FIFO Component's Exported Signals in the Top-Level Platform Designer System
1.7.2.1. Opening an Existing Intel® Quartus® Prime Project and the kernel_system.qsys Platform Designer System Design
1.7.2.2. Adding an Avalon® -ST Adapter Component into the Platform Designer System
1.7.2.3. Connecting the Avalon® -ST Adapter Component's Exported Signals in the Top-Level Platform Designer System
1.7.2.4. Modifying the board_spec.xml File
1.7.2.5. Modifying the freeze_wrapper.v File
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1.3. Hierarchical Structure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform's Hardware
The Intel® Arria® 10 GX FPGA Development Kit Reference Platform consists of four main blocks, as implemented in a Intel® Quartus® Prime project.
Figure 2. Hierarchical Structure of the OpenCL Hardware System on an Intel® Arria® 10 Device
Root Partition (top.v)
The top.v file describes the I/O ring of the FPGA, which specifies in RTL all of the interfaces to which the FPGA will connect on the PCB.
Board Interface (board.qsys)
The board.qsys file is a Platform Designer representation of the Reference Platform. This Platform Designer representation contains IP such as external memory interface (EMIF) to connect to external memory, and hard processor system (HPS) to act as an internal host. When modifying an existing platform, you must update the board.qsys file. This file typically contains the logic for the interfaces which are described in the top.v file.
Freeze Wrapper (freeze_wrapper.v)
The freeze_wrapper.v file is used for Partial Reconfiguration (PR). If your design does not use PR, this file simply acts as a wrapper around the OpenCL kernel. You must change the freeze_wrapper.v file if you wish to modify an existing platform that connects to the kernel. Refer to the Kernel Reprogramming via Partial Reconfiguration section of the Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide for more details on how to implement the freeze wrapper.
OpenCL Kernel (kernel_system.qsys)
When the SDK user compiles an OpenCL kernel, the Intel® FPGA SDK for OpenCL™ Offline Compiler creates the kernel_system.qsys file as part of the compilation flow. The SDK user designs this Platform Designer representation of the kernel to optimize its performance when using the FPGA as a hardware acceleration engine.