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1.1. Introduction to Custom Platforms
1.2. OpenCL System Architecture
1.3. Hierarchical Structure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform's Hardware
1.4. Intel® Quartus® Prime Software Revisions Describing the Custom Platform
1.5. Intel® FPGA SDK for OpenCL™ and User Environment Setup
1.6. Intel® Arria® 10 Custom Platform Project Setup and Customization Procedure
1.7. Intel® Arria® 10 Custom Platform Customization Example
1.8. Updating Your Custom Platform to Target a Different Device
1.9. Migrating the Custom Platform between Different Intel® Quartus® Prime Software Versions
1.10. Document Revision History for Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL*
1.7.1. Modifying the board.qsys File in the Custom Platform
1.7.2. Modifying the Kernel (freeze_wrapper.v and board_spec.xml)
1.7.3. Updating the Top-Level I/O Ring with the Modified board.qsys and freeze_wrapper.v Files
1.7.4. Updating the Original Custom Platform Directory with the New Custom Platform Modifications
1.7.5. Compilation Log Files
1.7.6. Analyzing the Results from Compilation
1.7.1.1. Opening an Existing Intel® Quartus® Prime Project and the board.qsys Platform Designer System Design
1.7.1.2. Adding the Avalon® -ST Single Clock FIFO Component into the Platform Designer System
1.7.1.3. Connecting the Avalon® -ST Single Clock FIFO Component's Exported Signals in the Top-Level Platform Designer System
1.7.2.1. Opening an Existing Intel® Quartus® Prime Project and the kernel_system.qsys Platform Designer System Design
1.7.2.2. Adding an Avalon® -ST Adapter Component into the Platform Designer System
1.7.2.3. Connecting the Avalon® -ST Adapter Component's Exported Signals in the Top-Level Platform Designer System
1.7.2.4. Modifying the board_spec.xml File
1.7.2.5. Modifying the freeze_wrapper.v File
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1.7.4. Updating the Original Custom Platform Directory with the New Custom Platform Modifications
The final step to customizing your Custom Platform is to copy all modified files back into the original Custom Platform directory (that is, the a10gx_ref_18.1/hardware/a10gx_fifo directory). By updating the files in the a10gx_fifo directory, the Intel® FPGA SDK for OpenCL™ Offline Compiler will use the new customized Custom Platform when it performs subsequent compilations that target your Intel® Arria® 10 board.
- Copy the following files back into the hardware/a10gx_fifo directory.
Table 8. Files to be Copied into the hardware/a10gx_fifo Directory Files Changes ROOT PARTITION top.v Added extra ports between the board and freeze wrapper components. BOARD INTERFACE board.qsys Added a FIFO component to the Platform Designer framework. base.qar Copied and replaced the base.qar file from the current directory back into the hardware/a10gx_fifo directory. FREEZE WRAPPER FILES freeze_wrapper.v Added extra ports for the FIFO component that is part of the kernel logic. - After modifying the files in the original Custom Platform directory, regenerate your new Custom Platform by performing the following tasks:
- Ensure that the vector_add.cl file is in the a10gx_ref_18.1 project directory. If not, download the design example and copy the vector_add.cl file to the a10gx_ref_18.1 directory.
- At a command prompt, invoke the aoc vector_add.cl –v --no-interleaving default command to compile the vector_add kernel to hardware. If the Intel® FPGA SDK for OpenCL™ Offline Compiler reports any errors, refer to the Compilation Log Files section for more information that can help you debug your kernel.
- After the Intel® FPGA SDK for OpenCL™ Offline Compiler finishes compiling the vector_add kernel, refer to the Analyzing the Results from Compilation section to check the Fitter, Timing Analyzer reports and placement in the Floorplanner.