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1.1. Generating Primary Device Programming Files
1.2. Generating Secondary Programming Files
1.3. Enabling Bitstream Security for Intel® Stratix® 10 Devices
1.4. Enabling Bitstream Encryption or Compression for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
1.5. Generating Programming Files for Partial Reconfiguration
1.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems
1.7. Scripting Support
1.8. Generating Programming Files Revision History
2.1. Intel® Quartus® Prime Programmer
2.2. Programming and Configuration Modes
2.3. Basic Device Configuration Steps
2.4. Specifying the Programming Hardware Setup
2.5. Programming with Flash Loaders
2.6. Verifying the Programming File Source with Project Hash
2.7. Using PR Bitstream Security Verification ( Intel® Stratix® 10 Designs)
2.8. Stand-Alone Programmer
2.9. Programmer Settings Reference
2.10. Scripting Support
2.11. Using the Intel® Quartus® Prime Programmer Revision History
2.9.1. Device & Pin Options Dialog Box
2.9.2. More Security Options Dialog Box
2.9.3. Output Files Tab Settings (Programming File Generator)
2.9.4. Input Files Tab Settings (Programming File Generator)
2.9.5. Bitstream Co-Signing Security Settings (Programming File Generator)
2.9.6. Configuration Device Tab Settings
2.9.7. Add Partition Dialog Box (Programming File Generator)
2.9.8. Convert Programming File Dialog Box
2.9.9. Compression and Encryption Settings (Convert Programming File)
2.9.10. SOF Data Properties Dialog Box (Convert Programming File)
2.9.11. Select Devices (Flash Loader) Dialog Box
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1.2.1.2. Secondary Programming Files (Programming File Generator)
After generating primary device programming files, you can generate the following secondary device programming files with the Programming File Generator for alternative device configuration modes:
Programming File Type | Extension | Description |
---|---|---|
Hexadecimal ( Intel® -Format) Output File for SRAM | .hexout | An ASCII text file in Intel® hexadecimal format that contains configuration data for programming a parallel data source, such as a configuration device or a mass storage device. The parallel data source in turn configures an SRAM-based Intel device. |
JTAG Indirect Configuration File | .jic | Proprietary Intel® FPGA file type that stores serial flash programming data for programming via Intel® FPGA JTAG pins. This method only supports Active Serial configuration. Before programming the flash, the Programmer first configures the FPGA with the Serial Flash Helper Design. |
Map File | .map | A text file containing the byte addresses of pages and data stored in the memory of a configuration device for |
Programmer Object File | .pof | A binary file used by the Programmer to program a flash memory device via active serial header, or to program a flash memory device via the Parallel Flash Loader Intel FPGA IP. |
Raw Binary File | .rbf | Configuration bitstream file for use with a third-party data source, partial reconfiguration, or HPS data source. Supports Passive Serial (PS) and Avalon® -Streaming (AVST) modes. |
Raw Binary File for CvP Core Configuration | .rbf | A binary file that containing logic that is programmed by configuration (CRAM) for CvP phase 2. The core bitstream is in .rbf format. |
Raw Binary File for HPS Core Configuration | A binary file that containing logic that is programmed by configuration (CRAM) for HPS configuration phase 2. The core bitstream is in .rbf format. | |
Raw Programming Data File | .rpd | Stores data for configuration with third-party programming hardware. You generate Raw Programming Data Files from a .pof or .sof. The .rpd file is a subset of a .pof or .jic that includes only device-specific binary programming data for Active Serial configuration scheme with EPCS or EPCQ serial configuration devices and remote system update. |
Tabular Text File | .ttf | A TTF contains the decimal equivalent of a Raw Binary File (.rbf). |