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1.1. Generating Primary Device Programming Files
1.2. Generating Secondary Programming Files
1.3. Enabling Bitstream Security for Intel® Stratix® 10 Devices
1.4. Enabling Bitstream Encryption or Compression for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
1.5. Generating Programming Files for Partial Reconfiguration
1.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems
1.7. Scripting Support
1.8. Generating Programming Files Revision History
2.1. Intel® Quartus® Prime Programmer
2.2. Programming and Configuration Modes
2.3. Basic Device Configuration Steps
2.4. Specifying the Programming Hardware Setup
2.5. Programming with Flash Loaders
2.6. Verifying the Programming File Source with Project Hash
2.7. Using PR Bitstream Security Verification ( Intel® Stratix® 10 Designs)
2.8. Stand-Alone Programmer
2.9. Programmer Settings Reference
2.10. Scripting Support
2.11. Using the Intel® Quartus® Prime Programmer Revision History
2.9.1. Device & Pin Options Dialog Box
2.9.2. More Security Options Dialog Box
2.9.3. Output Files Tab Settings (Programming File Generator)
2.9.4. Input Files Tab Settings (Programming File Generator)
2.9.5. Bitstream Co-Signing Security Settings (Programming File Generator)
2.9.6. Configuration Device Tab Settings
2.9.7. Add Partition Dialog Box (Programming File Generator)
2.9.8. Convert Programming File Dialog Box
2.9.9. Compression and Encryption Settings (Convert Programming File)
2.9.10. SOF Data Properties Dialog Box (Convert Programming File)
2.9.11. Select Devices (Flash Loader) Dialog Box
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2.9.3. Output Files Tab Settings (Programming File Generator)
The Output Files tab allows you to specify the type of secondary programming file that you want to generate (output) with the Programming File Generator. The Programming File Generator converts a primary programming file (for example, .sof) into a programming file for alternative programming methods (for example, a .jic for flash programming). The Output Files tab and options change dynamically according to your selections.
The following output file options are available:
Setting | Description |
---|---|
Device family | Specifies the FPGA device family you are targeting for configuration. Programming File Generator supports only Intel® Agilex™ , Intel® Stratix® 10, Intel® MAX® 10, and Intel® Cyclone® 10 LP devices. |
Configuration mode | Specifies the method of FPGA configuration, such as Active Serial x4, AVST x8, AVST x16, or AVST x32. Generic Flash Programmer supports only Active Serial x4. |
Output directory and Name | Specifies the name and location of the file you generate. By default, this location is in the top-level project directory. |
File Types | Allows you to enable the type of secondary programming file that you want to generate. Generic Flash Programmer supports only JTAG Indirect Configuration File (.jic). The available options include:
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