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1.1. Generating Primary Device Programming Files
1.2. Generating Secondary Programming Files
1.3. Enabling Bitstream Security for Intel® Stratix® 10 Devices
1.4. Enabling Bitstream Encryption or Compression for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
1.5. Generating Programming Files for Partial Reconfiguration
1.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems
1.7. Scripting Support
1.8. Generating Programming Files Revision History
2.1. Intel® Quartus® Prime Programmer
2.2. Programming and Configuration Modes
2.3. Basic Device Configuration Steps
2.4. Specifying the Programming Hardware Setup
2.5. Programming with Flash Loaders
2.6. Verifying the Programming File Source with Project Hash
2.7. Using PR Bitstream Security Verification ( Intel® Stratix® 10 Designs)
2.8. Stand-Alone Programmer
2.9. Programmer Settings Reference
2.10. Scripting Support
2.11. Using the Intel® Quartus® Prime Programmer Revision History
2.9.1. Device & Pin Options Dialog Box
2.9.2. More Security Options Dialog Box
2.9.3. Output Files Tab Settings (Programming File Generator)
2.9.4. Input Files Tab Settings (Programming File Generator)
2.9.5. Bitstream Co-Signing Security Settings (Programming File Generator)
2.9.6. Configuration Device Tab Settings
2.9.7. Add Partition Dialog Box (Programming File Generator)
2.9.8. Convert Programming File Dialog Box
2.9.9. Compression and Encryption Settings (Convert Programming File)
2.9.10. SOF Data Properties Dialog Box (Convert Programming File)
2.9.11. Select Devices (Flash Loader) Dialog Box
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2.2. Programming and Configuration Modes
The current version of the Intel® Quartus® Prime Programmer supports the following programming and configuration modes in the Programmer's Mode list. Select a configuration mode to setup and run that type of programming or configuration.
Programming or Configuration Mode | Description |
---|---|
JTAG | A configuration method that configures one or more devices through the Joint Test Action Group (JTAG) Boundary-Scan Test (BST) circuitry. |
In-Socket Programming | Configuration device programming or testing via the Altera Programming Unit (APU). |
Passive Serial | An external controller passes configuration data to one or more configuration devices via a serial data stream. The device is treated as a slave device with a 5-wire interface to the external controller. The external controller can be an intelligent host such as a microcontroller or CPU, or the Intel® Quartus® Prime Programmer. The external controller can also be a serial configuration device. |
Active Serial Programming | The active serial memory interface block loads design data into one or more devices. The active serial memory interface block controls the configuration process, and configures all of the devices in the chain using the configuration data stored in an EPCS1, EPCS4, EPCS16, EPCS64, EPCQ, EPCQL, and third-party QSPI serial configuration devices. |