Intel® Quartus® Prime Pro Edition User Guide: Programmer

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ID 683039
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Intel® Quartus® Prime Programmer User Guide 2. Using the Intel® Quartus® Prime Programmer 3. Using the HPS Flash Programmer A. Intel® Quartus® Prime Pro Edition User Guide: Programmer Document Archive B. Intel® Quartus® Prime Pro Edition User Guides
1. Intel® Quartus® Prime Programmer User Guide x
1.1. Generating Primary Device Programming Files 1.2. Generating Secondary Programming Files 1.3. Enabling Bitstream Security for Intel® Stratix® 10 Devices 1.4. Enabling Bitstream Encryption or Compression for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.5. Generating Programming Files for Partial Reconfiguration 1.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems 1.7. Scripting Support 1.8. Generating Programming Files Revision History
1.2. Generating Secondary Programming Files x
1.2.1. Generating Secondary Programming Files (Programming File Generator) 1.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box) 1.2.3. Generating Secondary Programming Files (Settings: Programming Files Dialog Box)
1.2.1. Generating Secondary Programming Files (Programming File Generator) x
1.2.1.1. Configuration Modes (Programming File Generator) 1.2.1.2. Secondary Programming Files (Programming File Generator)
1.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box) x
1.2.2.1. Secondary Programming Files (Convert Programming Files) 1.2.2.2. Configuration Modes (Convert Programming Files) 1.2.2.3. Debugging the Configuration (Convert Programming Files)
1.3. Enabling Bitstream Security for Intel® Stratix® 10 Devices x
1.3.1. Enabling Bitstream Authentication (Programming File Generator) 1.3.2. Specifying Additional Physical Security Settings (Programming File Generator) 1.3.3. Enabling Bitstream Encryption (Programming File Generator)
1.5. Generating Programming Files for Partial Reconfiguration x
1.5.1. Generating PR Bitstream Files 1.5.2. Partial Reconfiguration Bitstream Compatibility Checking Intel® Stratix® 10 and Intel® Agilex™ PR Bitstream Compatibility Checking Intel® Arria® 10 and Intel® Cyclone® 10 GX PR Bitstream Compatibility Checking 1.5.3. Raw Binary Programming File Byte Sequence Transmission Examples 1.5.4. Generating a Merged .pmsf File from Multiple .pmsf Files ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)
1.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems x
1.6.1. Generating Programming Files for HPS Boot First Boot Flows 1.6.2. Generating Programming Files for FPGA Configuration First Boot Flows
1.7. Scripting Support x
1.7.1. quartus_pfg Command Line Tool 1.7.2. quartus_cpf Command Line Tool
1.7.2. quartus_cpf Command Line Tool x
1.7.2.1. Generating a Partial-Mask SRAM Object File using a Mask Settings File and a SRAM Object File
2. Using the Intel® Quartus® Prime Programmer x
2.1. Intel® Quartus® Prime Programmer 2.2. Programming and Configuration Modes 2.3. Basic Device Configuration Steps 2.4. Specifying the Programming Hardware Setup 2.5. Programming with Flash Loaders 2.6. Verifying the Programming File Source with Project Hash 2.7. Using PR Bitstream Security Verification ( Intel® Stratix® 10 Designs) 2.8. Stand-Alone Programmer 2.9. Programmer Settings Reference 2.10. Scripting Support 2.11. Using the Intel® Quartus® Prime Programmer Revision History
2.4. Specifying the Programming Hardware Setup x
2.4.1. JTAG Chain Debugger Tool 2.4.2. Editing the Details of an Unknown Device 2.4.3. Running JTAG Daemon with Linux
2.4.1. JTAG Chain Debugger Tool x
2.4.1.1. JTAG Chain Integrity Tab 2.4.1.2. JTAG Chain Debugging Tab
2.5. Programming with Flash Loaders x
2.5.1. Specifying Flash Partitions 2.5.2. Full Erase of Flash Memory Sectors
2.6. Verifying the Programming File Source with Project Hash x
2.6.1. Obtaining Project Hash for Intel® Arria® 10 Devices
2.8. Stand-Alone Programmer x
2.8.1. Stand-Alone Programmer Memory Consumption
2.9. Programmer Settings Reference x
2.9.1. Device & Pin Options Dialog Box 2.9.2. More Security Options Dialog Box 2.9.3. Output Files Tab Settings (Programming File Generator) 2.9.4. Input Files Tab Settings (Programming File Generator) 2.9.5. Bitstream Co-Signing Security Settings (Programming File Generator) 2.9.6. Configuration Device Tab Settings 2.9.7. Add Partition Dialog Box (Programming File Generator) 2.9.8. Convert Programming File Dialog Box 2.9.9. Compression and Encryption Settings (Convert Programming File) 2.9.10. SOF Data Properties Dialog Box (Convert Programming File) 2.9.11. Select Devices (Flash Loader) Dialog Box
2.10. Scripting Support x
2.10.1. The jtagconfig Debugging Tool
3. Using the HPS Flash Programmer x
3.1. HPS Flash Programmer Command-Line Utility 3.2. How the HPS Flash Programmer Works 3.3. Using the Flash Programmer from the Command Line 3.4. Supported Memory Devices 3.5. HPS Flash Programmer User Guide Revision History
3.3. Using the Flash Programmer from the Command Line x
3.3.1. HPS Flash Programmer 3.3.2. HPS Flash Programmer Command Line Examples
1. Intel® Quartus® Prime Programmer User Guide
2. Using the Intel® Quartus® Prime Programmer
3. Using the HPS Flash Programmer
A. Intel® Quartus® Prime Pro Edition User Guide: Programmer Document Archive
B. Intel® Quartus® Prime Pro Edition User Guides

1.5.2. Partial Reconfiguration Bitstream Compatibility Checking

Partial reconfiguration bitstream compatibility checking verifies the compatibility of the reconfiguration bitstream to prevent configuration with an incompatible PR bitstream. The following sections describe PR bitstream compatibility check support.
Figure 20. PR Bitstream Compatibility Checking

Intel® Stratix® 10 and Intel® Agilex™ PR Bitstream Compatibility Checking

For Intel® Stratix® 10 and Intel® Agilex™ designs, PR bitstream compatibility checking is automatically enabled in the Compiler and in the Secure Device Manager (SDM) firmware by default. The following limitations apply to PR designs if PR bitstream compatibility checking is enabled:

  • The firmware allows up to a total of 32 PR regions, irrespective of the number of hierarchical partial reconfiguration layers.
  • Your PR design can have up to six hierarchical partial reconfiguration layers.
  • Your PR design, when there is no hierarchy, can have up to 32 regions.
  • Your PR design can have up to 15 child PR regions of any parent PR region (if it is hierarchical). Child PR regions count towards the total limit of 32 PR regions.

The Compiler generates an error if your PR design exceeds these limits when PR bitstream compatibility checking is enabled.

If you require more PR regions than this limitation allows, or otherwise want to disable PR bitstream compatibility checking , you can add the following assignment to the .qsf file: 
set_global_assignment -name ENABLE_PR_POF_ID OFF
When you set this assignment to off, the limit of 32 total regions does not apply in the Compiler.
Note: If you require the PR bitstream authentication feature for your design, you must enable PR bitstream compatibility checking by setting the global assignment ENABLE_PR_POF ID to ON. The default setting is ON.

Intel® Arria® 10 and Intel® Cyclone® 10 GX PR Bitstream Compatibility Checking

For Intel® Arria® 10 and Intel® Cyclone® 10 GX designs, you enable or disable PR bitstream compatibility checking by turning on the Enable bitstream compatibility check option when instantiating the Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP from the IP Catalog.

The PR IP verifies the partial reconfiguration PR Bitstream file (.rbf). When you enable the bitstream compatibility check, the PR .pof ID is encoded as the 71st word of the PR bitstream. If the PR IP detects an incompatible bitstream, then the PR IP stops the PR operation, and the status output reports an error.

When you turn on Enable bitstream compatibility check, the PR Controller IP core creates a PR bitstream ID and displays the bitstream ID in the configuration dialog box. For bitstream compatibility checking with hierarchical PR designs, refer to additional steps in AN 806: Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 GX FPGA Development Board.

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