Visible to Intel only — GUID: mwh1410385108828
Ixiasoft
1.1. Generating Primary Device Programming Files
1.2. Generating Secondary Programming Files
1.3. Enabling Bitstream Security for Intel® Stratix® 10 Devices
1.4. Enabling Bitstream Encryption or Compression for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
1.5. Generating Programming Files for Partial Reconfiguration
1.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems
1.7. Scripting Support
1.8. Generating Programming Files Revision History
2.1. Intel® Quartus® Prime Programmer
2.2. Programming and Configuration Modes
2.3. Basic Device Configuration Steps
2.4. Specifying the Programming Hardware Setup
2.5. Programming with Flash Loaders
2.6. Verifying the Programming File Source with Project Hash
2.7. Using PR Bitstream Security Verification ( Intel® Stratix® 10 Designs)
2.8. Stand-Alone Programmer
2.9. Programmer Settings Reference
2.10. Scripting Support
2.11. Using the Intel® Quartus® Prime Programmer Revision History
2.9.1. Device & Pin Options Dialog Box
2.9.2. More Security Options Dialog Box
2.9.3. Output Files Tab Settings (Programming File Generator)
2.9.4. Input Files Tab Settings (Programming File Generator)
2.9.5. Bitstream Co-Signing Security Settings (Programming File Generator)
2.9.6. Configuration Device Tab Settings
2.9.7. Add Partition Dialog Box (Programming File Generator)
2.9.8. Convert Programming File Dialog Box
2.9.9. Compression and Encryption Settings (Convert Programming File)
2.9.10. SOF Data Properties Dialog Box (Convert Programming File)
2.9.11. Select Devices (Flash Loader) Dialog Box
Visible to Intel only — GUID: mwh1410385108828
Ixiasoft
2.10. Scripting Support
In addition to the Intel® Quartus® Prime Programmer GUI, you can access programmer functionality from the command line and from scripts with the Intel® Quartus® Prime command-line executable quartus_pgm.exe (or quartus_pgm in Linux).
The following command programs a device from a Microsoft* Windows* command line:
quartus_pgm –c usbblasterII –m jtag –o bpv;design.pof
Where:
- -c usbblasterII
- specifies the Intel® FPGA Download Cable II
- -m jtag
- specifies the JTAG programming mode
- -o bpv
- represents the blank-check, program, and verify operations
- design.pof
- represents the .pof containing the design logic
The Programmer automatically executes the erase operation before programming the device.
In a Linux* terminal terminal window, use:
quartus_pgm –c usbblasterII –m jtag –o bpv\;design.pof
The following examples shows how to erase flash memory that is connected to the FPGA through an active serial interface from a Microsoft* Windows* command line:
quartus_pgm -c usbblasterII -m jtag -o ri;design.jic@1
Where:
- -c usbblasterII
- specifies the Intel® FPGA Download Cable II
- -m jtag
- specifies the JTAG programming mode
- -o ri
- represents the serial flash loader program and erase operations
- design.jic
- represents the JTAG indirect configuration file (.jic)
- @1
- specifies the device number in the JTAG chain on which these operations are performed
In a Linux* terminal terminal window, use:
quartus_pgm -c usbblasterII -m jtag -o ri\;design.jic@1
Related Information