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1.1. Generating Primary Device Programming Files
1.2. Generating Secondary Programming Files
1.3. Enabling Bitstream Security for Intel® Stratix® 10 Devices
1.4. Enabling Bitstream Encryption or Compression for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
1.5. Generating Programming Files for Partial Reconfiguration
1.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems
1.7. Scripting Support
1.8. Generating Programming Files Revision History
2.1. Intel® Quartus® Prime Programmer
2.2. Programming and Configuration Modes
2.3. Basic Device Configuration Steps
2.4. Specifying the Programming Hardware Setup
2.5. Programming with Flash Loaders
2.6. Verifying the Programming File Source with Project Hash
2.7. Using PR Bitstream Security Verification ( Intel® Stratix® 10 Designs)
2.8. Stand-Alone Programmer
2.9. Programmer Settings Reference
2.10. Scripting Support
2.11. Using the Intel® Quartus® Prime Programmer Revision History
2.9.1. Device & Pin Options Dialog Box
2.9.2. More Security Options Dialog Box
2.9.3. Output Files Tab Settings (Programming File Generator)
2.9.4. Input Files Tab Settings (Programming File Generator)
2.9.5. Bitstream Co-Signing Security Settings (Programming File Generator)
2.9.6. Configuration Device Tab Settings
2.9.7. Add Partition Dialog Box (Programming File Generator)
2.9.8. Convert Programming File Dialog Box
2.9.9. Compression and Encryption Settings (Convert Programming File)
2.9.10. SOF Data Properties Dialog Box (Convert Programming File)
2.9.11. Select Devices (Flash Loader) Dialog Box
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1.1. Generating Primary Device Programming Files
By default, the Compiler's Assembler module generates the primary device programming files at the end of full compilation. Alternatively, you can start the Assembler independently any time after design place and route to generate primary device programming files, such as SRAM Object Files (.sof) for configuration of Intel® FPGAs.
Follow these steps to generate primary device programming files:
- To specify programming options that enable features in the primary device programming file, such as Configuration, Error Detection CRC, and device Security options, click Assignments > Device > Device & Pin Options. Device & Pin Options Dialog Box describes all options.1
Figure 2. Device & Pin Options Dialog Box ( Intel® Stratix® 10 Design)
- To generate primary device programming files, click Processing > Start > Start Assembler, or double-click Assembler on the Compilation Dashboard. The Assembler generates the programming files according to the options you specify.
- After running the Assembler, view detailed information about programming file generation, including the programming file Summary and Encrypted IP information in the Assembler report folder in the Compilation Report.
Figure 3. Assembler ReportsNote: Each successive release of the Intel® Quartus® Prime software typically includes:
- Added support for new features in supported FPGA devices.
- Added support for new devices.
- Efficiency and performance improvements.
- Improvements to compilation time and resource use of the design software.
1 Security options not yet available for Intel® Agilex™ devices.