2.9.1. Device & Pin Options Dialog Box
Option | Description |
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Options
Note: Not supported for Intel® Agilex™ or Intel® Stratix® 10 devices.
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Auto usercode | Sets the JTAG user code to match the checksum value of the device programming file. The programming file is a .pof for non-volatile devices, or an .sof for SRAM-based devices. If you turn on this option, the JTAG user code option is not available. |
JTAG user code | Specifies a hexadecimal number for the device selected for the current Compiler settings. The JTAG user code is an extension of the option register. This data can be read with the JTAG USERCODE instruction. If you turn on Auto usercode, this option is not available. |
In-system programming clamp state | Allows you to specify the state that the pins take during in-system programming for used pins that do not have an in-system programming clamp state assignment. Unused pins and dedicated inputs must always be tri-stated for in-system programming. Used pins are tri-stated by default during in-system programming, which electrically isolates the device from other devices on the board. At times, however, in order to prevent system damage you may want to specify the logic level for used pins during in-system programming. The following settings are available:
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Configuration clock source | Specifies the clock source for device initialization (the duration between CONF_DONE signal went high and before INIT_DONE signal goes high). For AS x1 or AS x4 configuration mode, you can select either Internal Oscillator or CLKUSR pin only. The DCLK pin is an illegal option for AS mode. In 14 nm device families, only Internal Oscillator or OSC_CLK_1 pins are available. |
Device initialization clock source | Specifies the clock source for device initialization (the duration between CONF_DONE signal went high and before INIT_DONE signal goes high). For AS x1 or AS x4 configuration mode, you can select either Internal Oscillator or CLKUSR pin only. The DCLK pin is an illegal option for AS mode. In 14 nm device families, only Internal Oscillator or OSC_CLK_1 pins are available. |
Option | Description |
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Configuration scheme | Specifies the scheme of configuration for generation of appropriate primary and secondary programming files, such as Active Serial x4. Only options appropriate for the current Configuration Scheme are available. |
Configuration Device | Allows you to specify options for an external configuration device that stores and loads configuration data.
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Configuration Pin Options | Enables or disables operation of specific device configuration pins for status monitoring, SEU error detection, CvP, and other configuration pin options. |
Generate compressed bitstreams | Generates compressed bitstreams and enables bitstream decompression in the target device. |
Active serial clock source | Specifies the configuration clock source for Active Serial programming. Options range from 12.5 MHz to 100 MHz. |
VID Operation Mode | Enables Voltage IDentification logic in the target device with selected operation mode. The available options are PMBus Master or PMBus Slave. |
HPS/FPGA configuration order | For hard processor system (HPS) configuration, specifies the order of configuration between the HPS and FPGA. The options are HPS First, After INIT_DONE, and When requested by FPGA. |
HPS debug access port |
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Disable Register Power-Up Initialization | Specifies whether the Assembler generates a bit stream with register power-up initialization. |
Option | Description |
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Reserve all unused pins |
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Option | Description |
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Dual-purpose pins |
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Option | Description |
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I/O standard | Specifies the supported I/O standard, such as Differential 1.8-V SSTL Class II. |
Board trace model | Lists the board trace model parameters, with units, and values for the specified I/O standard. You can change the value of each parameter. The board trace model assignments apply to all output and bidirectional pins with the specified I/O standard assigned to them. |
Option | Description |
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Default timing I/O endpoint | Specify Near end or Far end. |
Option | Description |
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Default I/O standard | Specify 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 LVTTL, or 3.0 LVCMOS. |
Option | Description |
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Enable Error Detection CRC_ERROR pin | Enables error detection CRC and CRC_ERROR pin usage for the targeted device. This check determines the validity of the programming data in the device. Any changes in the data while the device is in operation generates an error.
Note: Not available for Intel® Agilex™ or Intel® Stratix® 10 devices.
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Enable Open Drain on CRC Error pin | Sets the CRC ERROR pin as an open-drain pin. This action decouples the voltage level of the CRC ERROR pin from VCCIO voltage. When you turn on this option, you must connect a pull-up resistor to the CRC ERROR pin.
Note: Not available for Intel® Agilex™ or Intel® Stratix® 10 devices.
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Enable error detection check | Enables error detection CRC checking to verify the validity of programming data in the device, and reports any changes in the data while the device is in operation. |
Minimum SEU interval | Specifies the minimum time interval between two checks of the same bit. Setting to 0 means check as frequently as possible. Setting to a large value saves power. The unit of interval is millisecond. The maximum allowed number of intervals is 10000. |
Enable internal scrubbing | Specifies use of internal scrubbing to correct any detected single error or double adjacent error within the core configuration memory while the device is still running. |
Generate SEU sensitivity map file | Generates a Single Event Upset Sensitivity Map file. This file allows you to enable the Advanced SEU detection feature. |
Allow SEU fault injection | Allows the injection of fault patterns to test for SEU. |
Option | Description |
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Configuration via protocol | In Initialization and update mode, the periphery image stores in an external configuration device and loads the image into the FPGA through a conventional configuration scheme. The core image stores in a host memory and loads into the FPGA through the PCIe link. In Core initialization mode, the periphery image stores in an external configuration device and loads into the FPGA through the conventional configuration scheme. The core image is stores in a host memory and is loads into the FPGA through the PCIe link. In Core update mode, the FPGA device is initialized after initial system power up by loading the full configuration image from the external local configuration device to the FPGA. You can use the PCIe link to perform one or more FPGA core image update through this mode. In the Off mode, CvP is turned off. |
Enable CvP_CONFDONE pin | Indicates that the device finished core programming in Configuration via Protocol mode. If this option is turned off, the CvP_CONFDONE pin is disabled when the device operates in user mode and is available as a user I/O pin.
Note: Not available for Intel® Agilex™ or Intel® Stratix® 10 devices.
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Enable open drain on CvP_CONFDONE pin | Enables the open drain on the CvP_CONFDONE pin.
Note: Not available for Intel® Agilex™ or Intel® Stratix® 10 devices.
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Option | Description |
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Enable partial reconfiguration pins | Allows you to enable the PR_REQUEST, PR_READY, PR_ERROR, PR_DONE, DCLK, and DATA[31..0] pins. These pins are needed to support partial reconfiguration (PR) with an external host. An external host uses the PR_REQUEST pin to request partial reconfiguration, the PR_READY pin to determine if the device is ready to receive programming data, the PR_ERROR pin to externally monitor programming errors, and the PR_DONE pin to indicate the device finished programming. If this option is turned off, these pins are not available as PR pins when the device operates in user mode and the dual-purpose programming pins are available as user I/O pins.
Note: Not available for Intel® Agilex™ or Intel® Stratix® 10 devices.
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Enable open drain on partial reconfiguration pins | Allows you to specify an open drain on the PR_READY, PR_ERROR, PR_DONE Partial Reconfiguration pins.
Note: Not available for Intel® Agilex™ or Intel® Stratix® 10 devices.
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Generate Partial-Masked SOF files | Generates a Partial-Masked SRAM Object file (.pmsf) containing both configuration data and region definitions that can be used to re-configure a device region. If this option is turned on, the .pmsf generates instead of a Mask Settings file (.msf). |
Generate Partial Reconfiguration RBF | Generates a Partial Reconfiguration Raw Binary File (.rbf) containing configuration data that an intelligent external controller can use to reconfigure the portion of target device. |
Option | Description |
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Bus speed mode | Specifies the bus speed mode (for example, 100 KHz or 400 KHz) in PMBus Master mode. |
Slave device type | Specifies the slave device type when the target FPGA device is in PMBus master mode. Available options are ED8401, EM21XX, EM22XX, ISL82XX, LTM4677, and Other. |
Device address in PMBus Slave mode | Specifies the starting 00 device address when in PMBus Slave mode. |
PMBus device 0 slave address through PMBus device 7 slave address | Specifies 7-bit hexadecimal value (without leading prefix 0x). For example, 7F for the slave address of a voltage regulator when in PMBus Master mode. You must specify a non-zero address. |
Voltage output format | Specifies the Auto discovery, Direct format, or Linear format output voltage format when in PMBus Master mode |
Direct format coefficient (m,b,R) | Specifies direct format coefficient m, b, or R when in PMBus Master mode. Signed integer between -32768 and 32767. Coefficient m is the slope coefficient. Coefficient b is the offset. Coefficient R is the exponent. Refer to the PMBus device manufacturer product documentation for these values. You must set this parameter when output voltage format of PMBus device is Direct format or Auto discovery format. You must specify a non-zero address when the output voltage format of PMBus device is in Direct format. |
Linear format N | Specifies linear format N when in PMBus Master mode. Signed integer between -16 and 15. This is the exponent for the mantissa for the output voltage related command when VOUT format is set to Linear format. Refer to the PMBus device manufacturer product documentation for these values. You must specify a non-zero value for Linear format. |
Translated voltage value unit | Specifies the Volts or Millivolts output voltage format when in PMBus Master mode. |
Enable PAGE command | The FPGA PMBus master uses PAGE command to set all output channels on registered regulator modules to respond to VOUT_COMMAND. |
Option | Description |
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Quartus Key File | Specifies the first level signature chain file (.qky) that you generate. This chain includes the root key (.pem) and one or more design signing keys (.pem) required to sign the bitstream and allow access to the FPGA when using authentication or encryption. |
Encryption key storage select | Specifies the location that stores the .qek key file. You can select either Battery Backup RAM or eFuses for storage. |
Encryption update ratio | Specifies the ratio of configuration bits compared to the number of key updates required for bitstream decryption. You can select either 31:1 (the key must change 1 time every 31 bits) or Disabled (no update required). Encryption supports up to 20 intermediate keys. |
Enable scrambling | Scrambles the configuration bitstream. |
More Options | Opens the More Security Options dialog box for specifying additional physical security options. |
Option | Values | Description |
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USE PWRMGT_SCL output | SDM_1O0| SDM_IO14 | This is a required PMBus interface for the power management when the VID operation mode is the PMBus Master or PMBus Slave mode. Disable this pin for a non-SmartVID device. Intel® recommends using the SDM_IO14 pin for this function. |
Use PWRMGT_SDA output | SDM_1O11| SDM_1O12|SDM_1O16 | This is a required PMBus interface for the power management when the VID operation mode is the PMBus Master or PMBus Slave mode. Disable this pin for a non-SmartVID device. Intel® recommends using the SDM_IO11 pin for this function. |
Use PWRMGT_ALERT output | SDM_1O0|SDM_1O12 | This is a required PMBus interface for the power management that is used only in the PMBus Slave mode. Disable this pin for a non-SmartVID device. Intel® recommends using the SDM_IO12 pin for this function. |
USE CONF_DONE output | SDM_100, SDM_1010 - SDM_1016 | Implement CONF_DONE using appropriate configuration pin resource. |
USE INIT_DONE output | SDM_100, SDM_1010 - SDM_1016 | Enables the INIT_DONE pin, which allows you to externally monitor when initialization is completed and the device is in user mode. If this option is turned off, the INIT_DONE pin is disabled when the device operates in user mode and is available as a user I/O pin. |
USE CVPCONF_DONE output | SDM_100, SDM_1010 - SDM_1016 | Enables the CVP_CONFDONE pin, which indicates that the device finished core programming in Configuration via Protocol mode. If this option is turned off, the CVP_CONFDONE pin is disabled when the device operates in user mode and is available as a user I/O pin. |
USE SEU_ERROR output | SDM_100, SDM_1010 - SDM_1016 | Enables the SEU_ERROR pin for use in single event upset error detection. |
USE UIB CATTRIP output | SDM_100, SDM_1010 - SDM_1016 | Enables UIB_CATTRIP output to indicate an extreme over-temperature conditioning resulted from UIB usage. |
USE HPS cold nreset | SDM_100, SDM_1010 - SDM_1016 | An optional reset input that cold resets only the HPS and is configured for bidirectional operation. |
Direct to factory image | SDM_100, SDM_1010 - SDM_1016 | If this pin asserted then device loads the factory image as the first image after boot without attempting to load any application image. |
USE DATA LOCK output | SDM_100, SDM_1010 - SDM_1016 | Output to indicate DIBs on both die in the same package is ready for data transfer. |