Intel® Quartus® Prime Pro Edition User Guide: Programmer

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ID 683039
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Intel® Quartus® Prime Programmer User Guide 2. Using the Intel® Quartus® Prime Programmer 3. Using the HPS Flash Programmer A. Intel® Quartus® Prime Pro Edition User Guide: Programmer Document Archive B. Intel® Quartus® Prime Pro Edition User Guides
1. Intel® Quartus® Prime Programmer User Guide x
1.1. Generating Primary Device Programming Files 1.2. Generating Secondary Programming Files 1.3. Enabling Bitstream Security for Intel® Stratix® 10 Devices 1.4. Enabling Bitstream Encryption or Compression for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.5. Generating Programming Files for Partial Reconfiguration 1.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems 1.7. Scripting Support 1.8. Generating Programming Files Revision History
1.2. Generating Secondary Programming Files x
1.2.1. Generating Secondary Programming Files (Programming File Generator) 1.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box) 1.2.3. Generating Secondary Programming Files (Settings: Programming Files Dialog Box)
1.2.1. Generating Secondary Programming Files (Programming File Generator) x
1.2.1.1. Configuration Modes (Programming File Generator) 1.2.1.2. Secondary Programming Files (Programming File Generator)
1.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box) x
1.2.2.1. Secondary Programming Files (Convert Programming Files) 1.2.2.2. Configuration Modes (Convert Programming Files) 1.2.2.3. Debugging the Configuration (Convert Programming Files)
1.3. Enabling Bitstream Security for Intel® Stratix® 10 Devices x
1.3.1. Enabling Bitstream Authentication (Programming File Generator) 1.3.2. Specifying Additional Physical Security Settings (Programming File Generator) 1.3.3. Enabling Bitstream Encryption (Programming File Generator)
1.5. Generating Programming Files for Partial Reconfiguration x
1.5.1. Generating PR Bitstream Files 1.5.2. Partial Reconfiguration Bitstream Compatibility Checking 1.5.3. Raw Binary Programming File Byte Sequence Transmission Examples 1.5.4. Generating a Merged .pmsf File from Multiple .pmsf Files ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)
1.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems x
1.6.1. Generating Programming Files for HPS Boot First Boot Flows 1.6.2. Generating Programming Files for FPGA Configuration First Boot Flows
1.7. Scripting Support x
1.7.1. quartus_pfg Command Line Tool 1.7.2. quartus_cpf Command Line Tool
1.7.2. quartus_cpf Command Line Tool x
1.7.2.1. Generating a Partial-Mask SRAM Object File using a Mask Settings File and a SRAM Object File
2. Using the Intel® Quartus® Prime Programmer x
2.1. Intel® Quartus® Prime Programmer 2.2. Programming and Configuration Modes 2.3. Basic Device Configuration Steps 2.4. Specifying the Programming Hardware Setup 2.5. Programming with Flash Loaders 2.6. Verifying the Programming File Source with Project Hash 2.7. Using PR Bitstream Security Verification ( Intel® Stratix® 10 Designs) 2.8. Stand-Alone Programmer 2.9. Programmer Settings Reference 2.10. Scripting Support 2.11. Using the Intel® Quartus® Prime Programmer Revision History
2.4. Specifying the Programming Hardware Setup x
2.4.1. JTAG Chain Debugger Tool 2.4.2. Editing the Details of an Unknown Device 2.4.3. Running JTAG Daemon with Linux
2.4.1. JTAG Chain Debugger Tool x
2.4.1.1. JTAG Chain Integrity Tab 2.4.1.2. JTAG Chain Debugging Tab
2.5. Programming with Flash Loaders x
2.5.1. Specifying Flash Partitions 2.5.2. Full Erase of Flash Memory Sectors
2.6. Verifying the Programming File Source with Project Hash x
2.6.1. Obtaining Project Hash for Intel® Arria® 10 Devices
2.8. Stand-Alone Programmer x
2.8.1. Stand-Alone Programmer Memory Consumption
2.9. Programmer Settings Reference x
2.9.1. Device & Pin Options Dialog Box 2.9.2. More Security Options Dialog Box 2.9.3. Output Files Tab Settings (Programming File Generator) 2.9.4. Input Files Tab Settings (Programming File Generator) 2.9.5. Bitstream Co-Signing Security Settings (Programming File Generator) 2.9.6. Configuration Device Tab Settings 2.9.7. Add Partition Dialog Box (Programming File Generator) 2.9.8. Convert Programming File Dialog Box 2.9.9. Compression and Encryption Settings (Convert Programming File) 2.9.10. SOF Data Properties Dialog Box (Convert Programming File) 2.9.11. Select Devices (Flash Loader) Dialog Box
2.10. Scripting Support x
2.10.1. The jtagconfig Debugging Tool
3. Using the HPS Flash Programmer x
3.1. HPS Flash Programmer Command-Line Utility 3.2. How the HPS Flash Programmer Works 3.3. Using the Flash Programmer from the Command Line 3.4. Supported Memory Devices 3.5. HPS Flash Programmer User Guide Revision History
3.3. Using the Flash Programmer from the Command Line x
3.3.1. HPS Flash Programmer 3.3.2. HPS Flash Programmer Command Line Examples
1. Intel® Quartus® Prime Programmer User Guide
2. Using the Intel® Quartus® Prime Programmer
3. Using the HPS Flash Programmer
A. Intel® Quartus® Prime Pro Edition User Guide: Programmer Document Archive
B. Intel® Quartus® Prime Pro Edition User Guides

3.3.1. HPS Flash Programmer

The HPS flash programmer utility can erase, blank-check, program, verify, and examine the flash. The utility accepts a Binary File with a required ".bin" extension.

The HPS flash programmer command-line syntax is: 

quartus_hps <options> <file.bin>
Note: The HPS flash programmer uses byte addressing.
Table 40.  HPS Flash Programmer Parameters
Option Short Option Required Description
--addr -a

Yes (if the start address is not 0)

This option specifies the start address of the operation to be performed.

--cable -c

Yes

This option specifies what download cable to use.

To obtain the list of programming cables, run the command "jtagconfig". It lists the available cables, like in the following example:
jtagconfig
  • Intel® FPGA Download Cable [USB-0]
  • Intel® FPGA Download Cable [USB-1]
  • Intel® FPGA Download Cable [USB-2]
The "-c" parameter can be the number of the programming cable, or its name. The following are valid examples for the above case:
  • -c 1
  • -c " Intel® FPGA Download Cable [USB-2]"
--device -d

Yes (if there are multiple HPS devices in the chain)

This option specifies the index of the HPS device. The tool automatically detects the chain and determine the position of the HPS device; however, if there are multiple HPS devices in the chain, the targeted device index must be specified.

--boot N/A Yes

Option to reconfigure the HPS IOCSR and PINMUX before starting flash programming.

For the Intel® Quartus® Prime HPS Flash Programmer options:
  • Warm/cold reset HPS (BootROM) so that BootROM can reconfigure the setting.

    FPGA (for Intel® Arria® 10) is nconfig.

  • Explicitly configure dedicated I/O and PINMUX
Available options:
  • 1 - Set Breakpoint to halt CPU, warm reset HPS [not recommended]11
  • 2 - Set Watchpoint to halt CPU, warm reset HPS12
  • 3 - Explicitly configure dedicated IO and PINMUX13
  • 16 - Cold reset HPS14

Cyclone® V and Intel® Arria® 10 support values: 1, 2 and 16.

Intel® Arria® 10 supports values: 2, 3 and 16
Note: For the first three options, add up integer of 16, so that the HPS cold reset is performed
Available options for a cold reset before the flow:
  • 17 - Cold reset HPS + breakpoint15
  • 18 - Cold reset HPS + watchpoint16
  • 19 - Cold reset HPS + configure dedicated IO and PINMUX17
--exit_xip N/A Yes (if the QSPI flash device has been put into XIP mode) This option exits the QSPI flash device from XIP mode. A non-zero value has to be specified for the argument. For example, quartus_hps -c <cable> -o <operation> --exit_xip=0x80.
--operation -o

Yes

This option specifies the operation to be performed. The following operations are supported:

  • I—Read IDCODE of SOC device and discover Access Port
  • S—Read Silicon ID of the flash
  • E—Erase flash
  • B—Blank-check flash
  • P—Program flash
  • V—Verify flash
  • EB—Erase and blank-check flash
  • BP—Program <BlankCheck> flash
  • PV—Program and verify flash
  • BPV—Program (blank-check) and verify flash
  • X—Examine flash
Note: The program begins with erasing the flash operation before programming the flash by default.
--size -s

No

This option specifies the number of bytes of data to be performed by the operation. size is optional.

Note: The following options: repeat and interval must be used together and are optional.

The HPS BOOT flow supports up to four images where each image is identical. These options duplicate the operation data; therefore you do not need embedded software to create a large file containing duplicate images.

--repeat -t No repeat—specifies the number of duplicate images for the operation to perform.
--interval -i No interval—specifies the repeated address. The default value is 64 kilobytes (KB).
11 Warm reset HPS for BootROM to configure dedicated IO and PINMUX, and use a breakpoint to halt CPU.
12 Warm reset HPS for BootROM to configure dedicated IO and PINMUX, and use a watchpoint to halt CPU.
13 Explicitly configure dedicated IO and PINMUX.
14 Bit-wise on top of the flow, if you set the bit, the tool will perform cold reset first
15 Cold reset HPS for BootROM to configure dedicated IO and PINMUX, and use a breakpoint to halt CPU.
16 Cold reset HPS for BootROM to configure dedicated IO and PINMUX, and use a watchpoint to halt CPU.
17 Cold reset HPS, then explicitly configure dedicated IO and PINMUX.
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