Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683026
Date 4/10/2023
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10GBASE-R Ethernet Design Example 3. 10M/100M/1G/2.5G/10G Ethernet Design Example 4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature 5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature 6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 7. Interface Signals Description 8. Configuration Registers Description 9. Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Changing Target Device in Hardware Design Example 1.5. Compiling and Testing the Design in Hardware
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Compiling and Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
1.3.1. Procedure x
1.3.1.1. Updating PHY IP Design File Names
1.4. Changing Target Device in Hardware Design Example x
1.4.1. Procedure
1.5. Compiling and Testing the Design in Hardware x
1.5.1. Procedure 1.5.2. Hardware Setup
2. 10GBASE-R Ethernet Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking and Reset Scheme
2.5. Hardware Testing x
2.5.1. Test Cases 2.5.2. Configuring FIFO Depth for Avalon® Streaming Loopback 2.5.3. Running Avalon® Streaming Loopback Test Case with Jumbo Ethernet Packets
3. 10M/100M/1G/2.5G/10G Ethernet Design Example x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme 3.3.4. Timing Constraints
3.5. Hardware Testing x
3.5.1. Test Procedure
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Interface Signals 4.7. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking Scheme 4.3.3. Reset Scheme 4.3.4. Timing Constraints
4.4. Simulation x
4.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
4.5. Hardware Testing x
4.5.1. Test Procedure
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Interface Signals 5.7. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme 5.3.4. Timing Constraints
5.4. Simulation x
5.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
5.5. Hardware Testing x
5.5.1. Changing to SFP+ Setting 5.5.2. Test Procedure
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
6.1. Features 6.2. Hardware and Software Requirements 6.3. Functional Description 6.4. Simulation 6.5. Hardware Testing 6.6. Interface Signals 6.7. Configuration Registers
6.3. Functional Description x
6.3.1. Design Components 6.3.2. Clocking Scheme 6.3.3. Reset Scheme
6.4. Simulation x
6.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 6.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
6.5. Hardware Testing x
6.5.1. Test Procedure
7. Interface Signals Description x
7.1. Clock and Reset Interface Signals 7.2. Avalon® Memory-Mapped Interface Signals 7.3. Avalon® Streaming Interface Signals 7.4. PHY Interface Signals 7.5. Status Interface 7.6. IEEE 1588v2 Timestamp Interface Signals 7.7. Packet Classifier Interface Signals 7.8. TOD Interface Signals
8. Configuration Registers Description x
8.1. Register Access Definition 8.2. Low Latency Ethernet 10G MAC 8.3. PHY 8.4. Transceiver Reconfiguration 8.5. TOD
8.3. PHY x
8.3.1. 1G/2.5G/5G/10G Multi-rate PHY
1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example
3. 10M/100M/1G/2.5G/10G Ethernet Design Example
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

5.3.4. Timing Constraints

When you configure the PHY in 1G/2.5G/10G (MGBASE-T) configuration, Intel® recommends that you refer to the Timing Constraints section of 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide for details on the timing constraint examples.

When the IEEE 1588v2 feature is enabled for 1G/2.5G/5G (MGBASE-T) PHY configuration, add the following constraints to the timing constraint file:

  • Set false path from native PHY 1G clock to 2.5G 1588 logic and vice versa. Since the 2.5G 1588 logic is not running the native 1G clock, you do not need to ensure timing closure for LL 10GbE MAC data path at 1G clock. For example:
    set_false_path -from [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile0|*}] \
               -to   [get_registers {*|alt_mge_1588_tod_2p5g:*|* \
                                     *|alt_mge_1588_tod_sync_*_2p5g:*|*}]
set_false_path -from [get_registers {*|alt_mge_1588_tod_2p5g:*|* \
                                     *|alt_mge_1588_tod_sync_*_2p5g:*|*}] \
               -to   [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile0|*}]
    where the path indicated by profile0 is associated to the native PHY 1G clock, whereas the alt_mge_1588_tod_2p5g and alt_mge_1588_tod_sync_*_2p5g paths indicate the 2.5G 1588 logic.
  • Set false path from native PHY 2.5G clock to 1G 1588 logic and vice versa. Since the 1G 1588 logic is not running the native 2.5G clock, you do not need to ensure timing closure for LL 10GbE MAC data path at 2.5G clock. For example:
    set_false_path -from [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile1|*}] \
               -to   [get_registers {*|alt_mge_1588_tod_1g:*|* \
                                     *|alt_mge_1588_tod_sync_*_1g:*|*}]
set_false_path -from [get_registers {*|alt_mge_1588_tod_1g:*|* \
                                     *|alt_mge_1588_tod_sync_*_1g:*|*}] \
               -to   [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile1|*}]
    where the path indicated by profile1 is associated to the native PHY 2.5G clock, whereas the alt_mge_1588_tod_1g and alt_mge_1588_tod_sync_*_1g paths indicate the 1G 1588 logic.
  • Set false path from native PHY 10G clock to 1G/2.5G 1588 logic and vice versa. Since the 1G/2.5G 1588 logic is not running the native 10G clock, you do not need to ensure timing closure for LL 10GbE MAC data path at 2.5G clock. For example:
    set_false_path -from [get_clocks \$profile2_clk] \\
                   -to   [get_registers *|alt_em10g32:*|*]
set_false_path -from [get_registers *|alt_em10g32:*|*] \\
                   -to   [get_clocks \$profile2_clk]
    where the path indicated by profile2 is associated to the native PHY 10G clock, whereas the alt_em10g32 path indicates the Low Latency Ethernet 10G MAC logic.
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