Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 4/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example

The 10M/100M/1G/2.5G/5G/10G (USXGMII) design example demonstrates an Ethernet solution for Intel® Stratix® 10 devices using the LL 10GbE MAC Intel® FPGA IP operating at 10M, 100M, 1G, 2.5G, 5G, and 10G.

Generate the design example from the Example Design tab of the LL 10GbE Intel® FPGA IP parameter editor. You can choose to generate the design with or without the IEEE 1588v2 feature.