Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683026
Date 4/10/2023
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10GBASE-R Ethernet Design Example 3. 10M/100M/1G/2.5G/10G Ethernet Design Example 4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature 5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature 6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 7. Interface Signals Description 8. Configuration Registers Description 9. Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Changing Target Device in Hardware Design Example 1.5. Compiling and Testing the Design in Hardware
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Compiling and Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
1.3.1. Procedure x
1.3.1.1. Updating PHY IP Design File Names
1.4. Changing Target Device in Hardware Design Example x
1.4.1. Procedure
1.5. Compiling and Testing the Design in Hardware x
1.5.1. Procedure 1.5.2. Hardware Setup
2. 10GBASE-R Ethernet Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking and Reset Scheme
2.5. Hardware Testing x
2.5.1. Test Cases 2.5.2. Configuring FIFO Depth for Avalon® Streaming Loopback 2.5.3. Running Avalon® Streaming Loopback Test Case with Jumbo Ethernet Packets
3. 10M/100M/1G/2.5G/10G Ethernet Design Example x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme 3.3.4. Timing Constraints
3.5. Hardware Testing x
3.5.1. Test Procedure
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Interface Signals 4.7. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking Scheme 4.3.3. Reset Scheme 4.3.4. Timing Constraints
4.4. Simulation x
4.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
4.5. Hardware Testing x
4.5.1. Test Procedure
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Interface Signals 5.7. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme 5.3.4. Timing Constraints
5.4. Simulation x
5.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
5.5. Hardware Testing x
5.5.1. Changing to SFP+ Setting 5.5.2. Test Procedure
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
6.1. Features 6.2. Hardware and Software Requirements 6.3. Functional Description 6.4. Simulation 6.5. Hardware Testing 6.6. Interface Signals 6.7. Configuration Registers
6.3. Functional Description x
6.3.1. Design Components 6.3.2. Clocking Scheme 6.3.3. Reset Scheme
6.4. Simulation x
6.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 6.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
6.5. Hardware Testing x
6.5.1. Test Procedure
7. Interface Signals Description x
7.1. Clock and Reset Interface Signals 7.2. Avalon® Memory-Mapped Interface Signals 7.3. Avalon® Streaming Interface Signals 7.4. PHY Interface Signals 7.5. Status Interface 7.6. IEEE 1588v2 Timestamp Interface Signals 7.7. Packet Classifier Interface Signals 7.8. TOD Interface Signals
8. Configuration Registers Description x
8.1. Register Access Definition 8.2. Low Latency Ethernet 10G MAC 8.3. PHY 8.4. Transceiver Reconfiguration 8.5. TOD
8.3. PHY x
8.3.1. 1G/2.5G/5G/10G Multi-rate PHY
1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example
3. 10M/100M/1G/2.5G/10G Ethernet Design Example
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

2.5.2. Configuring FIFO Depth for Avalon® Streaming Loopback

If you want to send Ethernet packets from external switch or tester with jumbo packet length such as 9600 bytes, you must increase the FIFO depth of the design example components.

These components are the CHANNEL[x].fifo_inst and CHANNEL[x].gen_mon_inst | avalon_st_loopback_u0 in the Avalon® streaming loopback path. The x index in the CHANNEL[x] are either 0 or 1.

To configure the FIFO depth of the design example components, follow these steps:

  1. Edit the rtl\eth_traffic_controller\avalon_st_loopback.sv file.
  2. Increase the value of the sc_fifo_depth parameter to increase the FIFO depth. Save the changes.
    Note: The default FIFO depth is 2048 and is sufficient to support 9600 bytes jumbo packets.

  3. In the Intel® Quartus® Prime Pro Edition software, on the the Project menu, select Upgrade IP Components.
  4. Select sc_fifo entity (IP Components: <Platform Designer>) from the list and click Upgrade in Editor. This launches the Platform Designer.
  5. At the FIFO depth parameter of both tx_sc_fifo and rx_sc_fifo components, increase the value of the FIFO depth from 1024 to 2048, for example.
  6. Click Generate HDL, then click Generate and Yes to save the changes and re-generate the SC FIFO IP. After the generation process is completed, exit the Platform Designer and close the Upgrade IP Components window.
  7. Perform full compilation of the design example.
  8. Edit the hw_testing\system_console\csr_pkg.tcl file.
    1. Add the following parameters under the MAC Address Map banner and save the changes:
      # RX path
set RX_MAX_FRAME_LENGTH_ADDR    0x00002004;   #Added to change max packet length
     
# TX path
set TX_MAX_FRAME_LENGTH_ADDR    0x00006004;   #Added to change max packet length
    2. If you want to test channel 1, add the following command before the if {![info exists CHANNEL]} { set CHANNEL 0 } command. Refer to the example in Setting Channel Number for Testing.
      set CHANNEL 1

      If you want to test channel 0, remove this command.

    Figure 11. Setting Channel Number for Testing
  9. Edit the hw_testing\system_console\config.tcl file.
    1. Comment out the Configure RX fifo section. Refer to the example below.
    2. Add commands to configure the TX and RX MAC's tx_frame_maxlength and rx_frame_maxlength Configuration and Status registers respectively to increase the maximum frame length without causing oversized frame error condition being triggered. Save the changes. Refer to the example in Example Command to Configure TX and RX MAC Maximum Frame Length .
      wr32 [expr {$CHANNEL*0x10000 + $MAC_BASE_ADDR}] $TX_MAX_FRAME_LENGTH_ADDR 0x0 0x2580   ;# 9600 bytes jumbo frame
wr32 [expr {$CHANNEL*0x10000 + $MAC_BASE_ADDR}] $RX_MAX_FRAME_LENGTH_ADDR 0x0 0x2580   ;# 9600 bytes jumbo frame
    Figure 12. Example Command to Configure TX and RX MAC Maximum Frame Length
When these steps are performed, the FIFO depth at both CHANNEL[0] and CHANNEL[1] in the Avalon® streaming loopback paths are increased. Follow the steps in Running Avalon Streaming Loopback Test Case with Jumbo Ethernet Packets to run the Avalon® streaming loopback test case.
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