Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 4/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.6. Interface Signals

Figure 44. Interface Signals of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example