Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683026
Date 4/10/2023
Public

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5.5. Hardware Testing

Follow the procedure at the provided link to test the design example in the selected hardware.

The design example is using QSFP28 IF1 by default. To use SFP+, follow instruction in Changing to SFP+ Setting.

In the Clock Controller application, which is part of the development kit, set the following frequencies:

For QSFP28 IF1 setting:
  • U5, OUT 5—644.53125 MHz
  • U5, OUT 4—125 MHz
  • U6, OUT 8—125 MHz
For SFP+ setting:
  • Y1—644.53125 MHz
  • U5, OUT 1—125 MHz
  • U5, OUT 8—125 MHz