Visible to Intel only — GUID: sfo1410067687992
Ixiasoft
Visible to Intel only — GUID: sfo1410067687992
Ixiasoft
3.3.3.3.2. SDRAM Clock Group
The SDRAM clock group consists of a PLL and clock gating. The clocks in the SDRAM clock group are derived from the SDRAM PLL. The SDRAM PLL can be programmed to be sourced from the HPS_CLK1 pin, the HPS_CLK2 pin, or the f2h_sdram_ref_clk clock provided by the FPGA fabric.
The FPGA fabric must be configured with an image that provides the f2h_sdram_ref_clk before selecting it as the clock source. If the FPGA must be reconfigured and the f2h_sdram_ref_clk is the clock source for the SDRAM clock group, an alternate clock source must be selected prior to reconfiguring the FPGA.
The counter outputs from the SDRAM PLL can be gated off directly under software control. The divider values for each clock are set by registers in the clock manager.
PLL | Output Counter | Clock Name | Frequency | Phase Shift Control |
---|---|---|---|---|
SDRAM | C0 | |
Varies 9 |
Yes |
C1 | |
ddr_dqs_base_clk x 2 | Yes | |
C2 | |
ddr_dqs_base_clk | Yes | |
C5 | |
osc1_clk to varies9 | Yes |
The following figure shows clock gating for SDRAM PLL clock group. Clock gate blocks in the diagram indicate clocks which may be gated off under software control. Software is expected to gate these clocks off prior to changing any PLL or divider settings that might create incorrect behavior on these clocks.
The SDRAM PLL output clocks can be phase shifted in real time in increments of 1/8 the VCO frequency. Maximum number of phase shift increments is 4096.
Name |
Frequency |
Constraints and Notes |
---|---|---|
|
SDRAM PLL C0 |
Clock for MPFE, single-port controller, CSR access, and PHY |
|
SDRAM PLL C1 |
Clock for PHY |
|
SDRAM PLL C2 |
Clock for PHY |
|
SDRAM PLL C5 |
Auxiliary user clock to the FPGA fabric |