Visible to Intel only — GUID: sfo1410068919826
Ixiasoft
Visible to Intel only — GUID: sfo1410068919826
Ixiasoft
18.3.1. HPS EMAC I/O Signals
The following table lists the EMAC signals that are routed to the HPS pins. These signals provide the RGMII interface.
EMAC Port |
In/Out |
Width |
Description |
|
---|---|---|---|---|
phy_txclk_o | Transmit Clock |
Out |
1 |
This signal provides the transmit clock for RGMII (125/25/2.5 MHz in 1G/100M/10Mbps). All PHY transmit signals generated by the EMAC are synchronous to this clock. |
phy_txd_o | PHY Transmit Data |
Out |
8 |
This group of eight transmit data signals is driven by the MAC. Bits [3:0] provide the RGMII transmit data. Unused bits in the RGMII interface configuration are tied low. In RGMII mode, the data bus carries transmit data at double rate and are sampled on both the rising and falling edges of the transmit clock. The validity of the data is qualified with phy_txen_o. |
phy_txen_o | PHY Transmit Data Enable |
Out |
1 |
This signal is driven by the EMAC component, and in RGMII mode acts as the control signal (rgmii_tctl) for the transmit data, and is driven on both edges of the transmit clock, phy_txclk_o. |
phy_clk_rx_i | Receive Clock |
In |
1 |
In RGMII mode, this clock frequency is 125/25/2.5 MHz in 1 G/100 M/10 Mbps modes. It is provided by the external PHY. All PHY signals received by the EMAC are synchronous to this clock. |
phy_rxd_i | PHY Receive Data |
In |
8 |
These eight data signals are received from the PHY and carry receive data at double rate with bits[3:0] valid on the rising edge of phy_rxclk_i, and bits[7:4] valid on the falling edge of phy_rxclk_i. The validity of the data is qualified with phy_rxdv_i. |
phy_rxdv_i | PHY Receive Data Valid |
In |
1 |
This signal is driven by the PHY and functions as the receive control signal used to qualify the data received on phy_rxd_i. This signal is sampled on both edges of the clock. Note that the signal phy_rxdv_i is assigned to pin RX_CTL in the device pin-out. |