Visible to Intel only — GUID: sfo1410070083891
Ixiasoft
Visible to Intel only — GUID: sfo1410070083891
Ixiasoft
27.2.1.1. User Clock Parameters
The frequencies that you provide are the maximum expected frequencies. The actual clock frequencies can be modified through the register interface, for example by software running on the microprocessor unit (MPU). For further details, refer to Selecting PLL Output Frequency and Phase.
Parameter Name |
Parameter Description |
Clock Interface Name |
---|---|---|
Enable HPS-to-FPGA user 0 clock |
Enable main PLL from HPS-to-FPGA |
|
User 0 clock frequency |
Specify the maximum expected frequency for the main PLL |
|
Enable HPS-to-FPGA user 1 clock |
Enable peripheral PLL from HPS-to-FPGA |
|
User 1 clock frequency |
Specify the maximum expected frequency for the peripheral PLL |
|
Enable HPS-to-FPGA user 2 clock | Enable SDRAM PLL from HPS-to-FPGA | h2f_user2_clock |
User 2 clock frequency | Specify the maximum expected frequency for the SDRAM PLL |