Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

3.3.7. Clock Usage By Module

The following table lists every clock input generated by the clock manager to all modules in the HPS. System clock names are global for the entire HPS and system clocks with the same name are phase-aligned at all endpoints.

Table 16.  Clock Usage By Module

Module Name

System Clock Name

Use

MPU subsystem

mpu_clk

Main clock for the MPU subsystem

mpu_periph_clk

Peripherals inside the MPU subsystem

dbg_at_clk

Trace bus

dbg_clk

Debug

mpu_l2_ram_clk

L2 cache and Accelerator Coherency Port (ACP) ID mapper

l4_mp_clk

ACP ID mapper control slave

Interconnect

l3_main_clk

L3 main switch

dbg_at_clk

System Trace Macrocell (STM) slave and Embedded Trace Router (ETR) master connections

dbg_clk

DAP master connection

l3_mp_clk

L3 master peripheral switch

l4_mp_clk

L4 MP bus, Secure Digital (SD) / MultiMediaCard (MMC) master, and EMAC masters

usb_mp_clk

USB masters and slaves

nand_x_clk

NAND master

cfg_clk

FPGA manager configuration data slave

l3_sp_clk

L3 slave peripheral switch

l3_main_clk

L4 SPIS bus master

mpu_l2_ram_clk

ACP ID mapper slave and L2 master connections

osc1_clk

L4 OSC1 bus master

spi_m_clk

L4 SPIM bus master

l4_sp_clk

L4 SP bus master

l4_mp_clk

Quad SPI bus slave

Boot ROM

l3_main_clk

Boot ROM

On-chip RAM

l3_main_clk

On-chip RAM

DMA controller

l4_main_clk

DMA

dbg_at_clk

Synchronous to the STM module

l4_mp_clk

Synchronous to the quad SPI flash

FPGA manager

cfg_clk

Control block (CB) data interface and configuration data slave

l4_mp_clk

Control slave

HPS‑to‑FPGA bridge

l3_main_clk

Data slave

l4_mp_clk

Global programmer's view (GPV) slave

FPGA‑to‑HPS bridge

l3_main_clk

Data master

l4_mp_clk

GPV slave

Lightweight HPS‑to‑FPGA bridge

l4_mp_clk

GPV masters and the data and GPV slave

Quad SPI flash controller

l4_mp_clk

Control slave

qspi_clk

Reference for serialization

SD/MMC controller

l4_mp_clk

Master and slave

sdmmc_clk

SD/MMC internal logic

EMAC 0

l4_mp_clk

Master

emac0_clk

EMAC 0 internal logic

osc1_clk

IEEE 1588 timestamp

EMAC 1

l4_mp_clk

Master

emac1_clk

EMAC 1 internal logic

osc1_clk

IEEE 1588 timestamp

USB 0

usb_mp_clk

Master and Slave

USB 1

usb_mp_clk

Master and Slave

NAND flash controller

nand_x_clk

NAND high-speed master and slave

nand_clk

NAND flash

OSC1 timer 0

osc1_clk

OSC1 timer 0

OSC1 timer 1

osc1_clk

OSC1 timer 1

SP timer 0

l4_sp_clk

SP timer 0

SP timer 1

l4_sp_clk

SP timer 1

I2C controller 0

l4_sp_clk

I2C 0

I2C controller 1

l4_sp_clk

I2C 1

I2C controller 2

l4_sp_clk

I2C 2

I2C controller 3

l4_sp_clk

I2C 3

UART controller 0

l4_sp_clk

UART 0

UART controller 1

l4_sp_clk

UART 1

GPIO interface 0

l4_mp_clk

Slave

gpio_db_clk

Debounce

GPIO interface 1

l4_mp_clk

Slave

gpio_db_clk

Debounce

GPIO interface 2

l4_mp_clk

Slave

gpio_db_clk

Debounce

System manager

osc1_clk 

System manager

SDRAM subsystem

l4_sp_clk

Control slave

ddr_dq_clk

Off-chip data

ddr_dqs_clk

MPFE, single-port controller, CSRs, and PHY

ddr_2x_dqs_clk

Off-chip strobe data

mpu_l2_ram_clk

Slave connected to MPU subsystem L2 cache

l3_main_clk

Slave connected to L3 interconnect

L4 watchdog timer 0

osc1_clk

L4 watchdog timer 0

L4 watchdog timer 1

osc1_clk

L4 watchdog timer 1

SPI master controller 0

spi_m_clk

SPI master 0

SPI master controller 1

spi_m_clk

SPI master 1

SPI slave controller 0

l4_main_clk

SPI slave 0

SPI slave controller 1

l4_main_clk

SPI slave 1

Debug subsystem

l4_mp_clk

System bus

dbg_clk

Debug

dbg_at_clk

Trace bus

dbg_trace_clk

Trace port

Reset manager

osc1_clk

Reset manager

l4_sp_clk

Slave

Scan manager

spi_m_clk

Scan manager

Timestamp generator

dbg_timer_clk

Timestamp generator