Visible to Intel only — GUID: sfo1410067695147
Ixiasoft
Visible to Intel only — GUID: sfo1410067695147
Ixiasoft
3.3.7. Clock Usage By Module
The following table lists every clock input generated by the clock manager to all modules in the HPS. System clock names are global for the entire HPS and system clocks with the same name are phase-aligned at all endpoints.
Module Name |
System Clock Name |
Use |
---|---|---|
MPU subsystem |
|
Main clock for the MPU subsystem |
|
Peripherals inside the MPU subsystem |
|
|
Trace bus |
|
|
Debug |
|
|
L2 cache and Accelerator Coherency Port (ACP) ID mapper |
|
|
ACP ID mapper control slave |
|
Interconnect |
|
L3 main switch |
|
System Trace Macrocell (STM) slave and Embedded Trace Router (ETR) master connections |
|
|
DAP master connection |
|
|
L3 master peripheral switch |
|
|
L4 MP bus, Secure Digital (SD) / MultiMediaCard (MMC) master, and EMAC masters |
|
|
USB masters and slaves |
|
|
NAND master |
|
|
FPGA manager configuration data slave |
|
|
L3 slave peripheral switch |
|
|
L4 SPIS bus master |
|
|
ACP ID mapper slave and L2 master connections |
|
|
L4 OSC1 bus master |
|
|
L4 SPIM bus master |
|
|
L4 SP bus master |
|
|
Quad SPI bus slave |
|
Boot ROM |
|
Boot ROM |
On-chip RAM |
|
On-chip RAM |
DMA controller |
|
DMA |
|
Synchronous to the STM module |
|
|
Synchronous to the quad SPI flash |
|
FPGA manager |
|
Control block (CB) data interface and configuration data slave |
|
Control slave |
|
HPS‑to‑FPGA bridge |
|
Data slave |
|
Global programmer's view (GPV) slave |
|
FPGA‑to‑HPS bridge |
|
Data master |
|
GPV slave |
|
Lightweight HPS‑to‑FPGA bridge |
|
GPV masters and the data and GPV slave |
Quad SPI flash controller |
|
Control slave |
|
Reference for serialization |
|
SD/MMC controller |
|
Master and slave |
|
SD/MMC internal logic |
|
EMAC 0 |
|
Master |
|
EMAC 0 internal logic |
|
|
IEEE 1588 timestamp |
|
EMAC 1 |
|
Master |
|
EMAC 1 internal logic |
|
|
IEEE 1588 timestamp |
|
USB 0 |
|
Master and Slave |
USB 1 |
|
Master and Slave |
NAND flash controller |
|
NAND high-speed master and slave |
|
NAND flash |
|
OSC1 timer 0 |
|
OSC1 timer 0 |
OSC1 timer 1 |
|
OSC1 timer 1 |
SP timer 0 |
|
SP timer 0 |
SP timer 1 |
|
SP timer 1 |
I2C controller 0 |
|
I2C 0 |
I2C controller 1 |
|
I2C 1 |
I2C controller 2 |
|
I2C 2 |
I2C controller 3 |
|
I2C 3 |
UART controller 0 |
|
UART 0 |
UART controller 1 |
|
UART 1 |
GPIO interface 0 |
|
Slave |
|
Debounce |
|
GPIO interface 1 |
|
Slave |
|
Debounce |
|
GPIO interface 2 |
|
Slave |
|
Debounce |
|
System manager |
|
System manager |
SDRAM subsystem |
|
Control slave |
|
Off-chip data |
|
|
MPFE, single-port controller, CSRs, and PHY |
|
|
Off-chip strobe data |
|
|
Slave connected to MPU subsystem L2 cache |
|
|
Slave connected to L3 interconnect |
|
L4 watchdog timer 0 |
|
L4 watchdog timer 0 |
L4 watchdog timer 1 |
|
L4 watchdog timer 1 |
SPI master controller 0 |
|
SPI master 0 |
SPI master controller 1 |
|
SPI master 1 |
SPI slave controller 0 |
|
SPI slave 0 |
SPI slave controller 1 |
|
SPI slave 1 |
Debug subsystem |
|
System bus |
|
Debug |
|
|
Trace bus |
|
|
Trace port |
|
Reset manager |
|
Reset manager |
|
Slave |
|
Scan manager |
|
Scan manager |
Timestamp generator |
|
Timestamp generator |