Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

A.7.1. Full Configuration

The HPS uses the FPGA manager to configure the FPGA portion of the device. The following sequence suggests one way for software to perform a full configuration:

  • CONF_DONE = 1 and nSTATUS = 1 indicates successful configuration.
  • CONF_DONE = 0 or nSTATUS = 0 indicates unsuccessful configuration. Complete steps 12 and 13, then go back and repeat steps 3 to 10 to reload the configuration image.
  • If DCLK is unused, write a value of 4 to the DCLK count register (dclkcnt).
  • If DCLK is used, write a value of 20,480 (0x5000) to the dclkcnt register.

If the HPS resets in the middle of a normal configuration data transfer before entering user mode, software can assume that the configuration is unsuccessful. After the HPS resets, software must repeat the steps for full configuration.

  1. Set the cdratio and cfgwdth bits of the ctrl register in the FPGA manager registers (fpgamgrregs) to match the characteristics of the configuration image. These settings are dependent on the MSEL pins input.
  2. Set the nce bit of the ctrl register to 0 to enable HPS configuration.
  3. Set the en bit of the ctrl register to 1 to give the FPGA manager control of the configuration input signals.
  4. Set the nconfigpull bit of the ctrl register to 1 to pull down the nCONFIG pin and put the FPGA portion of the device into the reset phase.
  5. Poll the mode bit of the stat register and wait until the FPGA enters the reset phase.
  6. Set the nconfigpull bit of the ctrl register to 0 to release the FPGA from reset.
  7. Read the mode bit of the stat register and wait until the FPGA enters the configuration phase.
  8. Clear the interrupt bit of nSTATUS (ns) in the gpio interrupt register ( fpgamgrregs.mon.gpio_porta_eoi).
  9. Set the axicfgen bit of the ctrl register to 1 to enable sending configuration data to the FPGA.
  10. Write the configuration image to the configuration data register (data) in the FPGA manager module configuration data registers (fpgamgrdata). You can also choose to use a DMA controller to transfer the configuration image from a peripheral device to the FPGA manager.
  11. Use the fpgamgrregs.mon.gpio_ext_porta registers to monitor the CONF_DONE (cd) and nSTATUS (ns) bits.
  12. Set the axicfgen bit of the ctrl register to 0 to disable configuration data on AXI slave.
  13. Clear any previous DONE status by writing a 1 to the dcntdone bit of the DCLK status register (dclkstat) to clear the completed status flag.
  14. Send the DCLKs required by the FPGA to enter the initialization phase.
  15. Poll the dcntdone bit of the DCLK status register (dclkstat) until it changes to 1, which indicates that all the DCLKs have been sent.
  16. Write a 1 to the dcntdone bit of the DCLK status register to clear the completed status flag.
  17. Read the mode bit of the stat register to wait for the FPGA to enter user mode.
  18. Set the en bit of the ctrl register to 0 to allow the external pins to drive the configuration input signals.