Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

27.1.5. AXI Bridges

Table 217.  Bridge Parameters

Parameter Name

Parameter Description

Interface Name

FPGA-to-HPS interface width

Enable or disable the FPGA-to-HPS interface; if enabled, set the data width to 32, 64, or 128 bits.

f2h_axi_slave

f2h_axi_clock

HPS-to-FPGA interface width

Enable or disable the HPS-to-FPGA interface; if enabled, set the data width to 32, 64, or 128 bits.

h2f_axi_master

h2f_axi_clock

Lightweight HPS-to-FPGA interface width

Enable or disable the lightweight HPS-to-FPGA interface. When enabled, the data width is 32 bits.

h2f_lw_axi_master

h2f_lw_axi_clock

Note: To facilitate accessing these slaves from a memory-mapped master with a smaller address width, you can use the Intel® Platform Designer (Standard) Address Span Extender.