Visible to Intel only — GUID: sfo1410069850895
Ixiasoft
Visible to Intel only — GUID: sfo1410069850895
Ixiasoft
22.4.6. Interrupts
The assertion of the UART interrupt output signal occurs when one of the following interrupt types are enabled and active: †
Interrupt Type |
Priority |
Source |
Interrupt Reset Control |
---|---|---|---|
Receiver line status |
Highest |
Overrun, parity and framing errors, break condition. |
Reading the line status Register. |
Received data available |
Second |
Receiver data available (FIFOs disabled) or RCVR FIFO trigger level reached (FIFOs enabled). |
Reading the receiver buffer register (FIFOs disabled) or the FIFO drops below the trigger level (FIFOs enabled) |
Character timeout indication |
Second |
No characters in or out of the Receive FIFO during the last 4 character times and there is at least 1 character in it during this Time. |
Reading the receiver buffer Register. |
Transmit holding register empty |
Third |
Transmitter holding register empty (Programmable THRE Mode disabled) or Transmit FIFO at or below threshold (Programmable THRE Mode enabled). |
Reading the IIR register (if source of interrupt); or, writing into THR (FIFOs or Programmable THRE Mode not enabled) or Transmit FIFO above threshold (FIFOs and Programmable THRE Mode enabled). |
Modem Status |
Fourth |
Clear to send or data set ready or ring indicator or data carrier detect. If auto flow control mode is enabled, a change in CTS (that is, DCTS set) does not cause an interrupt. |
Reading the Modem status Register. |
You can enable the interrupt types with the interrupt enable register (IER_DLH).
Once an interrupt is signaled, you can determine the interrupt source by reading the Interrupt Identity Register (IIR).