Visible to Intel only — GUID: sfo1410068323299
Ixiasoft
Visible to Intel only — GUID: sfo1410068323299
Ixiasoft
10.3.15. Accelerator Coherency Port
The ACP allows master peripherals—including FPGA-based peripherals—to maintain data coherency with the Cortex®-A9 MPCore* processors and the SCU. Dedicated master peripherals in the HPS, and those built in FPGA logic, access the coherent memory through the ACP ID mapper and the ACP.
The ACP port allows one-way coherency. One-way coherency allows an external ACP master to see the coherent memory of the Cortex®-A9 processors but does not allow the Cortex®-A9 processors to see memory changes outside of the cache.
- ACP master read with coherent data in the L1 cache: The ACP gets data directly from the L1 cache and the read is interleaved with a processor access to the L1 cache.
- ACP master read with coherent data in L2 cache: The ACP request is queued in the SCU and the transaction is sent to the L2 cache.
- ACP master read with coherent data not in L1 or L2 cache: Depending on the previous state of the data, the L1 or L2 cache may request the data from the L3 system interconnect. The ACP is stalled until data is available, however ACP support of multiple outstanding transactions minimizes bottlenecks.
- ACP master write with coherent data in the L1 cache: The L1 cache data is marked as invalid in the Cortex®-A9 MPU and the line is evicted from the L1 cache and sent to L2 memory. The ACP write data is scheduled in the SCU and is eventually written to the L2 cache. Later, when the Cortex®-A9 processor accesses the same memory location, a cache miss in the L1 occurs.
- ACP master write, with coherent data in the L2 cache: The ACP write is scheduled in the SCU and then is written into the L2 cache.
- ACP master write, with coherent data not in L1 or L2 cache: ACP write is scheduled.