Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

10.3.15.5. Exclusive and Locked Accesses

The ACP does not support exclusive accesses to coherent memory. Exclusive accesses to non-coherent memory can be generated, however, it is important that the exclusive access transaction is not affected by the upsizing and downsizing logic of the FPGA-to-HPS bridge or the system interconnect. If the exclusive access is broken into multiple transactions due to the sizing logic, the exclusive access bit is cleared by the bridge or interconnect and the exclusive access fails.

Note: Intel recommends that exclusive accesses bypass the ACP altogether, either through the 32‑bit slave port of the SDRAM controller connected directly to the system interconnect or through the FPGA-to-SDRAM interface.

The ACP ID mapper does not support locked accesses. To ensure mutually exclusive access to shared data, use the exclusive access support built into the SDRAM controller.