Visible to Intel only — GUID: GUID-837BBA1F-DAA6-409B-917F-216A1AE96C95
Visible to Intel only — GUID: GUID-837BBA1F-DAA6-409B-917F-216A1AE96C95
Synthesize Your RTL IP Core with Quartus Prime Software
When you are satisfied with the predicted performance of your kernel, use Quartus® Prime software to synthesize your kernel. Synthesis also generates accurate area and performance (fMAX) estimates for your design. However, your design is not expected to cleanly close timing in the Quartus® Prime reports.
You can expect to see timing closure warnings in the Quartus® Prime logs because the generated project targets a clock speed of 1000 MHz to achieve the best possible placement for your design. The fMAX value presented in the FPGA Optimization Report estimates the maximum clock rate your component can cleanly close timing for.
After the Quartus® Prime compilation is completed, the summary section of the FPGA Optimization Report shows the area and performance data for your kernels. These estimates are more accurate than estimates generated when you compile your kernel for simulation only.
Typically, Quartus® Prime compilation times can take minutes to hours, depending on the size and complexity of your kernel.
To synthesize your kernel and generate quality of results (QoR) data, instruct the compiler to run the Quartus® Prime compilation flow automatically after synthesizing the components. Include the –Xshardware option in your icpx command:
icpx -fintelfpga -Xshardware -Xstarget="<FPGA device family or part number>"...